公开(公告)号：US10431593B2

公开(公告)日：2019-10-01

申请号：US15860082

申请日：2018-01-02

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Sung-Min Hwang ,  Joon-Sung Lim ,  Kyoil Koo ,  Hoosung Cho ,  Sunyoung Kim ,  Cheol Ryou ,  Jaesun Yun

IPC: H01L27/11582 ,  H01L29/10 ,  H01L29/423 ,  H01L27/11565 ,  H01L27/1157

Abstract: Disclosed is a three-dimensional semiconductor memory device that includes first to third channel groups arranged in a first direction on a substrate. The first to third channel groups are spaced apart from each other along a second direction on the substrate. Each of the first to third channel groups includes a plurality of vertical channels that extend in a third direction perpendicular to a top surface of the substrate. The first and second channel groups are adjacent to each other in the second direction and spaced apart at a first distance in the second direction. The second and third channel groups are adjacent to each other in the second direction and are spaced apart at a second distance that is less than the first distance.

公开(公告)号：US10910398B2

公开(公告)日：2021-02-02

申请号：US16165426

申请日：2018-10-19

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jang-Gn Yun ,  Sunghoi Hur ,  Jaesun Yun ,  Joon-Sung Lim

IPC: H01L27/11582 ,  H01L27/11573 ,  H01L27/11575

Abstract: A semiconductor device may include a cell gate conductive pattern in a cell array area that extends to a step area, a cell vertical structure in the cell array area that extends through the cell gate conductive pattern, a cell gate contact structure on the cell gate conductive pattern in the step area, a cell gate contact region in the cell gate conductive pattern and aligned with the cell gate contact structure, a first peripheral contact structure spaced apart from the cell gate conductive pattern, a second peripheral contact structure spaced apart from the first peripheral contact structure, a first peripheral contact region under the first peripheral contact structure, and a second peripheral contact region under the second peripheral contact structure. The cell gate contact region may include a first element and a remainder of the cell gate conductive pattern may not substantially include the first element.

公开(公告)号：US10115667B2

公开(公告)日：2018-10-30

申请号：US14957113

申请日：2015-12-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jang-Gn Yun ,  Jaesun Yun ,  Joon-Sung Lim

IPC: H01L27/115 ,  H01L23/528 ,  H01L23/552 ,  H01L23/31 ,  H01L27/06 ,  H01L27/11573 ,  H01L27/11582

Abstract: A semiconductor device includes a cell semiconductor pattern disposed on a semiconductor substrate. A semiconductor dummy pattern is disposed on the semiconductor substrate. The semiconductor dummy pattern is co-planar with the cell semiconductor pattern. A first circuit is disposed between the semiconductor substrate and the cell semiconductor pattern. A first interconnection structure is disposed between the semiconductor substrate and the cell semiconductor pattern. A first dummy structure is disposed between the semiconductor substrate and the cell semiconductor pattern. Part of the first dummy structure is co-planar with part of the first interconnection structure. A second dummy structure not overlapping the cell semiconductor pattern is disposed on the semiconductor substrate. Part of the second dummy structure is co-planar with part of the first interconnection structure. A conductive shielding pattern is disposed between the cell semiconductor pattern and the semiconductor substrate and above the first circuit and the first interconnection structure.