公开(公告)号：US20230280782A1

公开(公告)日：2023-09-07

申请号：US18196242

申请日：2023-05-11

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyoung PARK ,  YOUNG-HOON SON ,  HYUN-YOON CHO ,  YOUNGDON CHOI ,  JUNGHWAN CHOI

IPC: G06F1/06 ,  G11C11/406 ,  G11C11/403 ,  G06F13/40

CPC classification number: G06F1/06 ,  G11C11/40607 ,  G11C11/403 ,  G06F13/4022

Abstract: Disclosed is a clock converting circuit, which includes a first switch that is connected between a first input node for receiving a second input clock and a first node and operates in response to a first logic state of a first input clock, the second input clock delayed with respect to the first input clock as much as 90 degrees, a second switch that is connected between a second input node for receiving the first input clock and a second node and operates in response to a second logic state of the second input clock, and a third switch that is connected between the second node and a ground node and operates in response to a first logic state of the second input clock opposite to the second logic state of the second input clock.

公开(公告)号：US20230223060A1

公开(公告)日：2023-07-13

申请号：US17939016

申请日：2022-09-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： BAEK JIN LIM ,  YOUNGCHUL CHO ,  SEUNGJIN PARK ,  DOOBOCK LEE ,  YOUNGDON CHOI ,  JUNGHWAN CHOI

IPC: G11C7/22 ,  G11C7/06 ,  G11C7/10

CPC classification number: G11C7/222 ,  G11C7/06 ,  G11C7/1096

Abstract: A semiconductor device according to an embodiment includes a plurality of sampler circuits configured to receive a plurality of offset clock signals or a plurality of divided clock signals and to sample a data signal in response to each of a plurality of divided clock signals. A calibration circuit applies a first offset clock signal to a first sampler circuit, applies a second offset clock signal having an opposite phase to the first offset clock signal to a second sampler circuit, and generates a first offset adjustment signal for adjusting an offset of the first sampler circuit based on an output of the first sampler circuit that is output in response to the first offset clock signal.

公开(公告)号：US20180166122A1

公开(公告)日：2018-06-14

申请号：US15889783

申请日：2018-02-06

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yoon-Joo EOM ,  JOON-YOUNG PARK ,  YONGCHEOL BAE ,  WON YOUNG LEE ,  SEONGJIN JANG ,  JUNGHWAN CHOI ,  JOOSUN CHOI

IPC: G11C11/4096 ,  G11C7/10 ,  G11C11/4093

CPC classification number: G11C11/4096 ,  G11C7/1084 ,  G11C11/4093 ,  G11C2207/105

Abstract: A multi channel semiconductor device is disclosed. The multi channel device may include a substrate, a first die on the substrate and having a first channel to function as a first chip; and a second die on the substrate and having a second channel different from the first channel to function as a second chip and including the same storage capacity and physical size as the first die. An internal interface is disposed between the first and second dies. The internal interface is configured to transmit information for controlling internal operations of the first and second dies and first applied to a first recipient die of the first and second dies to the other die.

公开(公告)号：US20160118090A1

公开(公告)日：2016-04-28

申请号：US14731787

申请日：2015-06-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： WON YOUNG LEE ,  YONGCHEOL BAE ,  JUNGHWAN CHOI

IPC: G11C7/10 ,  G11C11/4093 ,  G11C7/22

CPC classification number: G11C7/1087 ,  G11C7/1084

Abstract: Provided is a semiconductor device to prevent DC current from flowing between differential input signals. The semiconductor device includes a first input unit configured to buffer a first signal of differential input signals, a second input configured to buffer a second signal of the differential input signals, and a latch coupled between a first repeating node of the first input unit and a second repeating node of the second input unit to prevent duty variation of the first and second signals. The semiconductor device further includes a latch controller configured to selectively switch the operation of the latch based on states of the first and second signals appearing at the first and second repeating nodes during a time interval before preambles of the differential input signals are received.

Abstract translation: 提供了防止直流电流在差分输入信号之间流动的半导体器件。 半导体器件包括被配置为缓冲差分输入信号的第一信号的第一输入单元，被配置为缓冲差分输入信号的第二信号的第二输入，以及耦合在第一输入单元的第一中继节点与第一输入单元之间的锁存器 第二输入单元的第二重复节点，以防止第一和第二信号的占空比变化。 半导体器件还包括锁存器控制器，其被配置为基于在接收差分输入信号的前导码之前的时间间隔期间基于出现在第一和第二重复节点处的第一和第二信号的状态来选择性地切换锁存器的操作。