公开(公告)号：US12050988B2

公开(公告)日：2024-07-30

申请号：US18310008

申请日：2023-05-01

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungroh Yoon ,  Hyeokjun Choe ,  Seongsik Park ,  Seijoon Kim

IPC: G06N3/063 ,  G06F9/50 ,  G06F12/10

CPC classification number: G06N3/063 ,  G06F9/5016 ,  G06F9/5061 ,  G06F12/10

Abstract: A method of operating a storage device including a neural network processor includes outputting, by a controller device, a trigger signal instructing the neural network processor to perform a neural network operation in response to a command from a host device, requesting, by a neural network processor, target model data about parameters of a target model and instruction data for instructing the neural network operation to a memory device storing the target model data and the instruction data in response to the trigger signal, receiving, by the neural network processor, the target model data and the instruction data from the memory device and outputting, by the neural network processor, inference data based on the target model data and the instruction data.

公开(公告)号：US11962675B2

公开(公告)日：2024-04-16

申请号：US18299972

申请日：2023-04-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Younho Jeon ,  Hyeokjun Choe ,  Jeongho Lee

IPC: H04L69/22 ,  H04L69/04 ,  H04L69/08

CPC classification number: H04L69/22 ,  H04L69/04 ,  H04L69/08

Abstract: An interface circuit includes: a packet transmitter configured to generate a plurality of transmission packets based on a request, which is output from a core circuit, and output the plurality of transmission packets, the plurality of transmission packets including information indicative of being a packet to be merged; and a packet receiver configured to generate a merged packet by merging a plurality of extension packets from among a plurality of reception packets received from outside the interface circuit, the plurality of extension packets including information indicative of being a packet to be merged.

公开(公告)号：US11741034B2

公开(公告)日：2023-08-29

申请号：US17368981

申请日：2021-07-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Heehyun Nam ,  Jeongho Lee ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F13/28 ,  G06F3/06

CPC classification number: G06F13/28 ,  G06F3/0604 ,  G06F3/0655 ,  G06F3/0679 ,  G06F2213/28

Abstract: A memory device is configured to communicate with a plurality of host devices, through an interconnect, and includes a memory including a plurality of memory regions that includes a first memory region that is assigned to a first host device and a second memory region that is assigned to a second host device. The memory device further includes a direct memory access (DMA) engine configured to, based on a request from the first host device, the request including a copy command to copy data that is stored in the first memory region to the second memory region, read the stored data from the first memory region, and write the read data to the second memory region without outputting the read data to the interconnect.

公开(公告)号：US11669720B2

公开(公告)日：2023-06-06

申请号：US17230331

申请日：2021-04-14

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sungroh Yoon ,  Hyeokjun Choe ,  Seongsik Park ,  Seijoon Kim

IPC: G06N3/063 ,  G06F9/50 ,  G06F12/10

CPC classification number: G06N3/063 ,  G06F9/5016 ,  G06F9/5061 ,  G06F12/10

Abstract: A method of operating a storage device including a neural network processor includes outputting, by a controller device, a trigger signal instructing the neural network processor to perform a neural network operation in response to a command from a host device, requesting, by a neural network processor, target model data about parameters of a target model and instruction data for instructing the neural network operation to a memory device storing the target model data and the instruction data in response to the trigger signal, receiving, by the neural network processor, the target model data and the instruction data from the memory device and outputting, by the neural network processor, inference data based on the target model data and the instruction data.

公开(公告)号：US11586543B2

公开(公告)日：2023-02-21

申请号：US17380805

申请日：2021-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jeongho Lee ,  Heehyun Nam ,  Jaeho Shin ,  Hyodeok Shin ,  Younggeon Yoo ,  Younho Jeon ,  Wonseb Jeong ,  Ipoom Jeong ,  Hyeokjun Choe

IPC: G06F12/00 ,  G06F12/0817 ,  G06F3/06 ,  G06F12/0862

Abstract: A device connected to a host processor via a bus includes: an accelerator circuit configured to operate based on a message received from the host processor; and a controller configured to control an access to a memory connected to the device, wherein the controller is further configured to, in response to a read request received from the accelerator circuit, provide a first message requesting resolution of coherence to the host processor and prefetch first data from the memory.