公开(公告)号：US20210133543A1

公开(公告)日：2021-05-06

申请号：US16778168

申请日：2020-01-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JIN SOO LIM ,  CHANG KYU SEOL ,  JAE HUN JANG ,  HYE JEONG SO ,  HONG RAK SON ,  PIL SANG YOON

IPC: G06N3/063 ,  G06N20/00 ,  G06F7/544 ,  G11C11/419

Abstract: A storage device is provided including an interface circuit configured to receive application information from a host; a field programmable gate array (FPGA); a neural processing unit (NPU); and a central processing unit (CPU) configured to select a hardware image from among a plurality of hardware images stored in a memory using the application information, and reconfigure the FPGA using the selected hardware image. The NPU is configured to perform an operation using the reconfigured FPGA.

公开(公告)号：US20200050513A1

公开(公告)日：2020-02-13

申请号：US16357431

申请日：2019-03-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MINUK KIM ,  BOHWAN JUN ,  HONG RAK SON ,  DONG-MIN SHIN ,  KIJUN LEE

IPC: G06F11/10 ,  G06F3/06

Abstract: An operating method of a memory controller that individually controls a plurality of memory units includes reading respective segments from the plurality of memory units based on a plurality of control signals; generating an output codeword based on the segments; performing error correction decoding on the output codeword; when a result of the error correction decoding indicates success, updating at least one of a plurality of accumulated error pattern information respectively corresponding to the plurality of memory units based on the result of the error correction decoding; and when the result of the error correction decoding indicates failure, regulating at least one of the plurality of control signals based on at least one of the plurality of accumulated error pattern information.

公开(公告)号：US20190132010A1

公开(公告)日：2019-05-02

申请号：US16229153

申请日：2018-12-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DONG MIN SHIN ,  BEOM KYU SHIN ,  HEON HWA CHEONG ,  JUN JIN KONG ,  HONG RAK SON ,  YEONG GEOL SONG ,  SE JIN LIM

IPC: H03M13/39 ,  H03M13/11

CPC classification number: H03M13/3927 ,  H03M13/1117

Abstract: A method of operating a decoder, which has variable nodes and check nodes, includes receiving variable-to-check (V2C) messages from the variable nodes using a first check node among the check nodes. The number of messages having a specific magnitude among the V2C messages is counted. The magnitude of a check-to-variable (C2V) message to be transmitted to a first variable node, among the variable nodes, is determined based on the count value and the magnitude of a V2C message of the first variable node.

公开(公告)号：US20140281827A1

公开(公告)日：2014-09-18

申请号：US14208340

申请日：2014-03-13

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： MOSHE TWITTO ,  AVNER DOR ,  JUN JIN KONG ,  Chang Kyu SEOl ,  HONG RAK SON

IPC: G06F11/10

CPC classification number: G06F11/1072 ,  G06F11/108

Abstract: A method of processing data using a memory controller includes determining at least one cell state to which each of a plurality of multi-level cells can be changed to based on a current cell state of each multi-level cell, where each multi-level cell includes a plurality of data pages; determining one of the data pages as having a stuck bit when a value of the data page has a single mapping value based on mapping values mapped to the at least one cell state and generating stuck bit data regarding the stuck bit; and encoding write data to be stored in the multi-level cells based on the stuck bit data.

Abstract translation: 使用存储器控制器处理数据的方法包括基于每个多级单元的当前单元状态来确定可以改变多个多电平单元中的每一个的至少一个单元状态，其中每个多电平单元 包括多个数据页; 当数据页的值基于映射到所述至少一个单元状态的映射值具有单个映射值并且生成关于所述卡位的卡位位数据时，将所述数据页之一确定为具有卡住位; 以及基于所述卡住的位数据对要存储在所述多级单元中的写入数据进行编码。

公开(公告)号：US20140281293A1

公开(公告)日：2014-09-18

申请号：US14205496

申请日：2014-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANG KYU SEOL ,  JUN JIN KONG ,  HONG RAK SON

IPC: G06F12/02

CPC classification number: G11C11/5642 ,  G11C7/1006 ,  G11C11/5628 ,  G11C16/3418 ,  G11C2211/5632

Abstract: A method of operating a memory controller includes receiving a first data sequence and generating a coset representative sequence that can be divided into m-bit strings, where “m” is a natural number of at least 2; performing a first XOR operation on each of the m-bit strings in the coset representative sequence and binary bits; calculating all possible branch metrics according to a result of the first XOR operation; determining a survivor path sequence based on the all possible branch metrics; and performing a second XOR operation on the coset representative sequence and the survivor path sequence and generating an output sequence.

Abstract translation: 一种操作存储器控制器的方法包括：接收第一数据序列并产生可被划分成m位串的陪集代表序列，其中“m”是至少为2的自然数; 在陪集代表序列和二进制位中的每个m位串上执行第一异或运算; 根据第一异或运算的结果计算所有可能的分支度量; 基于所有可能的分支度量来确定幸存者路径序列; 以及对陪集代表序列和幸存者路径序列执行第二异或运算并产生输出序列。

公开(公告)号：US20140047246A1

公开(公告)日：2014-02-13

申请号：US13957652

申请日：2013-08-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： CHANGKYU SEOL ,  JUNJIN KONG ,  HONG RAK SON

IPC: G06F21/79

CPC classification number: G06F21/79 ,  G06F12/0246 ,  G06F12/1408 ,  G06F2212/7207

Abstract: A flash memory device is provided which includes a plurality of memory cells connected with a word line and including a key cell to store an encryption key; a data input/output circuit configured to receive the encryption key; and key control logic configured to control a program operation on the key cell and to use a column address of the key cell as the encryption key.

Abstract translation: 提供了一种闪存装置，其包括与字线连接的多个存储单元，并且包括用于存储加密密钥的密钥单元; 配置为接收加密密钥的数据输入/输出电路; 以及键控制逻辑，被配置为控制关键单元上的程序操作，并使用该键单元的列地址作为加密密钥。

公开(公告)号：US20130326314A1

公开(公告)日：2013-12-05

申请号：US13786509

申请日：2013-03-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： SEONGHYEOG CHOI ,  JUNJIN KONG ,  HONG RAK SON ,  PILSANG YOON

IPC: H03M13/37

CPC classification number: H03M13/3784 ,  H03M13/3707 ,  H03M13/45

Abstract: A storage device comprises a nonvolatile memory device comprising a plurality of memory cells, and an error correction circuit configured to receive primary data and secondary data from the nonvolatile memory device and to perform a hard decision decoding operation on the primary data and further configured to perform a soft decision decoding operation on the primary data based on the secondary data. The primary data is read from the plurality of memory cells in a hard decision read operation and the secondary data is read from memory cells programmed to a specific state from among the primary data.

Abstract translation: 存储装置包括包括多个存储器单元的非易失性存储器件，以及错误校正电路，被配置为从非易失性存储器件接收主数据和辅助数据，并对主数据进行硬判决解码操作，并进一步被配置为执行 基于次要数据对主数据进行软判决解码操作。 在硬判决读取操作中从多个存储器单元中读取主数据，并且从主数据中从被编程到特定状态的存储器单元读取次数据。

公开(公告)号：US20240072992A1

公开(公告)日：2024-02-29

申请号：US18312936

申请日：2023-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： YOUNG SIK MOON ,  JIYOUP KIM ,  HANBYEUL NA ,  HONG RAK SON ,  SEONGHYEOG CHOI

IPC: H04L9/00 ,  H04L9/08

CPC classification number: H04L9/008 ,  H04L9/0869

Abstract: A homomorphic encryption operator includes: a level configuration unit configured to set an encryption level by selecting a plurality of prime numbers of different values according to a scale factor condition used for multiplication of a homomorphic encryption operation and an increase/decrease condition for increasing or decreasing consecutively selected prime numbers, and a modular multiplication operator configured to perform lightweight modular multiplication using the selected plurality of prime numbers, wherein the level configuration unit includes: a level constructor configured to select prime number sets whose number have selected Hamming weights, respectively, based on the scale factor condition and the increase/decrease condition, and wherein the level configuration unit is further configured to configure the selected prime number sets with the encryption level using a prime number table.

公开(公告)号：US20230068302A1

公开(公告)日：2023-03-02

申请号：US17698639

申请日：2022-03-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： JAE HUN JANG ,  JI YOUP KIM ,  HAN BYEUL NA ,  YOUNG SUK RA ,  MAN KEUN SEO ,  HONG RAK SON ,  SE JIN LIM

IPC: G06F3/06

Abstract: A memory device includes an input unit configured to receive a plain text and output plain blocks and CTS plain block, a multi-core unit including a plurality of encryption/decryption cores configured to encrypt each of the plain blocks provided from the input unit and output cipher blocks in accordance with control of an encryption/decryption core control unit, a CTS core unit including a CTS core configured to encrypt the CTS plain block provided from the input unit into a CTS cipher block, and an output unit configured to receive the cipher blocks and the CTS cipher block and output a cipher text. The CTS plain block is generated through a CTS calculation based on the plain text.

公开(公告)号：US20210026734A1

公开(公告)日：2021-01-28

申请号：US16835721

申请日：2020-03-31

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNGJUN HWANG ,  DONG-MIN SHIN ,  CHANGKYU SEOL ,  JAEYONG SON ,  HONG RAK SON

IPC: G06F11/10 ,  G11C16/10 ,  G11C16/26

Abstract: A storage device includes a nonvolatile memory device that includes a plurality of pages, each of which includes a plurality of memory cells, and a controller that receives first write data expressed by 2m states (m being an integer greater than 1) from an external host device. The controller in a first operating mode shapes the first write data to second write data, which are expressed by “k” states (k being an integer greater than 2) smaller in number than the 2m states, performs first error correction encoding on the second write data to generate third write data expressed by the “k” states, and transmits the third write data to the nonvolatile memory device for writing at a selected page from the plurality of pages.