公开(公告)号：US20160005484A1

公开(公告)日：2016-01-07

申请号：US14856261

申请日：2015-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kyeong-Han Lee ,  Seok-Cheon Kwon ,  Dong-Yang Lee

IPC: G11C16/26 ,  G11C16/32 ,  G11C16/08

CPC classification number: G11C16/26 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C16/08 ,  G11C16/102 ,  G11C16/32 ,  G11C2207/107 ,  G11C2207/2281

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

公开(公告)号：US20160005482A1

公开(公告)日：2016-01-07

申请号：US14856182

申请日：2015-09-16

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： KYEONG-HAN LEE ,  Seok-Cheon Kwon ,  Dong-Yang Lee

IPC: G11C16/26 ,  G11C16/08 ,  G11C16/32

CPC classification number: G11C16/26 ,  G11C7/10 ,  G11C7/1018 ,  G11C7/1051 ,  G11C7/106 ,  G11C7/1066 ,  G11C7/22 ,  G11C7/222 ,  G11C16/08 ,  G11C16/102 ,  G11C16/32 ,  G11C2207/107 ,  G11C2207/2281

Abstract: A flash memory device including: a memory cell array; a signal generator inputting a first data fetch signal and outputting a second data fetch signal; and an output buffer circuit configured to output data from the memory cell array in sync with rising and falling edges of the second data fetch signal, wherein second data fetch signal is output along with data output from the output buffer circuit.

公开(公告)号：US09620180B2

公开(公告)日：2017-04-11

申请号：US14722158

申请日：2015-05-27

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sun-Young Lim ,  Dong-Yang Lee ,  Young-Jin Cho ,  Oh-Seong Kwon

IPC: G11C7/10

CPC classification number: G11C7/10 ,  G06F13/1694 ,  G11C7/1063 ,  G11C7/109

Abstract: An electronic device includes a memory controller; a first memory device coupled to the memory controller; a second memory device coupled to the memory controller, the second memory device being a different type of memory from the first memory device; and a conversion circuit between the memory controller and the second memory device. The memory controller is configured to send a first command and first data to the first memory device according to a first timing scheme to access the first memory device, and send a second command and a packet to the conversion circuit according to the first timing scheme to access the second memory device. The conversion circuit is configured to receive the second command and the packet, and access the second memory device based on the second command and the packet.

公开(公告)号：US09601218B2

公开(公告)日：2017-03-21

申请号：US14530951

申请日：2014-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Bu-Il Jung ,  Ju-Yun Jung ,  Do-Geun Kim ,  Dong-Yang Lee ,  Min-Yeab Choo

IPC: G11C29/00 ,  G11C29/44 ,  G06F9/44 ,  G11C29/04

CPC classification number: G11C29/44 ,  G06F9/4401 ,  G11C2029/0407 ,  G11C2029/4402

Abstract: A memory system includes a read-only memory (ROM), a main memory and a processor. The ROM stores a basic input/output system (BIOS). The main memory includes a fail address table which stores at least one fail address designating a memory cell row having at least one defective cell. The processor receives fail information of the at least one fail address from the main memory and loads data associated with a booting operation of the memory system in a safe area of the main memory by avoiding a fail area corresponding to the at least one fail address during power-on operation while a power is applied to the memory system. The data associated with the booting operation is stored in a storage device.