公开(公告)号：US20220207393A1

公开(公告)日：2022-06-30

申请号：US17468819

申请日：2021-09-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Naoto Umezawa ,  Changwook Jeong ,  Jisu Ryu ,  Kyu Hyun Lee ,  Jinyoung Lim ,  Wonik Jang ,  In Huh

IPC: G06N5/04 ,  G06N5/02

Abstract: Disclosed are methods of predicting semiconductor material properties and methods of testing semiconductor devices using the same. The prediction method comprises preparing a machine learning model that is trained with a training system and using the machine learning model to predict material properties of a target system. The machine learning model is represented as a function of material properties with respect to a descriptor. The descriptor is calculated from unrelaxed charge density (UCD) that is represented by summation of atomic charge density (ACD) of single atoms.

公开(公告)号：US12236178B2

公开(公告)日：2025-02-25

申请号：US17503558

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yohan Kim ,  Changwook Jeong ,  Jisu Ryu

IPC: G06F30/367 ,  G06F18/20 ,  G06F119/06 ,  G06N7/01

Abstract: A method of generating a circuit model used to simulate an integrated circuit may include generating first feature element data and second feature element data by classifying feature data of a target semiconductor device according to measurement conditions, generating first target data and second target data by preprocessing the first feature element data and the second feature element data, respectively, generating a first machine learning model using the first target data and extracting a second machine learning model using the second target data, and generating the circuit model used to simulate the integrated circuit using the first machine learning model and the second machine learning model.

公开(公告)号：US11982980B2

公开(公告)日：2024-05-14

申请号：US17230275

申请日：2021-04-14

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jinwoo Kim ,  Sanghoon Myung ,  Wonik Jang ,  Yongwoo Jeon ,  Kanghyun Baek ,  Jisu Ryu ,  Changwook Jeong

IPC: G05B13/04 ,  G05B13/02 ,  G06N3/045 ,  H01L27/02

CPC classification number: G05B13/042 ,  G05B13/027 ,  G06N3/045 ,  H01L27/0207

Abstract: According to an aspect of the present inventive concept, a simulation method for a semiconductor fabrication process includes obtaining, as input data, process parameters for controlling a semiconductor process of manufacturing semiconductor devices, or design parameters representing a structure of the semiconductor devices, or both the process parameters and the design parameters; generating predictive data for electrical characteristics of the semiconductor devices using a machine learning model based on the input data; generating reference data for the electrical characteristics of the semiconductor devices using a simulation tool based on the input data; and training the machine learning model using the predictive data and the reference data.

公开(公告)号：US20240086599A1

公开(公告)日：2024-03-14

申请号：US18509654

申请日：2023-11-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunjoong Kim ,  Jaepil Shin ,  Moonhyun Cha ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/045 ,  G06N3/08

CPC classification number: G06F30/27 ,  G06N3/045 ,  G06N3/08 ,  G06F2119/02

Abstract: A system for modeling a semiconductor fabrication process includes at least one first processor and at least one second processor. The at least one first processor is configured to provide at least one machine learning (ML) model, which is trained by using a plurality of pairs of images of a design pattern sample and a physical pattern sample. The physical pattern sample is formed from the design pattern sample by using the semiconductor fabrication process. The at least one second processor is configured to provide an input image representing a shape of a design pattern and/or a physical pattern to the at least one first processor and to generate output data defining the physical pattern and/or the design pattern based on an output image received from the at least one first processor.

公开(公告)号：US11886783B2

公开(公告)日：2024-01-30

申请号：US18153573

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon Myung ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

CPC classification number: G06F30/27 ,  G06F30/398 ,  G06N3/044 ,  G06N3/08 ,  G06N3/10

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

公开(公告)号：US11669773B2

公开(公告)日：2023-06-06

申请号：US16915786

申请日：2020-06-29

Applicant: Samsung Electronics Co., Ltd.

Inventor： Seungju Kim ,  Hyojin Choi ,  In Huh ,  Jeonghoon Ko ,  Changwook Jeong ,  Younsik Park ,  Joonwan Chai

IPC: G06N20/00 ,  G06F9/30 ,  G06F9/38 ,  G06F30/3308 ,  G06F18/214

CPC classification number: G06N20/00 ,  G06F9/30036 ,  G06F9/3879 ,  G06F18/214 ,  G06F30/3308

Abstract: An electronic device configured to generate a verification vector for verifying a semiconductor circuit including a first circuit block and a second circuit block includes a duplicate command eliminator configured to receive a first input vector including a plurality of commands and to provide a first converted vector, in which ones of the plurality of commands that generate the same state transition are changed into idle commands, based on a state transition of the first circuit block obtained by performing a simulation operation on the first input vector, a reduced vector generator configured to provide a first reduced vector in which a number of repetitions of the idle commands included in the first converted vector is reduced, and a verification vector generator configured to output the first reduced vector having a coverage that coincides with a target coverage among a plurality of first reduced vectors as a first verification vector.

公开(公告)号：US20230142367A1

公开(公告)日：2023-05-11

申请号：US18153573

申请日：2023-01-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon MYUNG ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-Chul Park ,  Changwook Jeong

IPC: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

CPC classification number: G06F30/27 ,  G06N3/08 ,  G06N3/10 ,  G06F30/398 ,  G06N3/044

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.

公开(公告)号：US20220121800A1

公开(公告)日：2022-04-21

申请号：US17503558

申请日：2021-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yohan Kim ,  Changwook Jeong ,  Jisu Ryu

IPC: G06F30/367 ,  G06N7/00 ,  G06K9/62

Abstract: A method of generating a circuit model used to simulate an integrated circuit may include generating first feature element data and second feature element data by classifying feature data of a target semiconductor device according to measurement conditions, generating first target data and second target data by preprocessing the first feature element data and the second feature element data, respectively, generating a first machine learning model using the first target data and extracting a second machine learning model using the second target data, and generating the circuit model used to simulate the integrated circuit using the first machine learning model and the second machine learning model.

公开(公告)号：US20210158152A1

公开(公告)日：2021-05-27

申请号：US16906038

申请日：2020-06-19

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sanghoon MYUNG ,  Hyunjae Jang ,  In Huh ,  Hyeon Kyun Noh ,  Min-chul Park ,  Changwook Jeong

IPC: G06N3/08 ,  G06N3/04 ,  G06N3/10

Abstract: Provided is a simulation method performed by a process simulator, implemented with a recurrent neural network (RNN) including a plurality of process emulation cells, which are arranged in time series and configured to train and predict, based on a final target profile, a profile of each process step included in a semiconductor manufacturing process. The simulation method includes: receiving, at a first process emulation cell, a previous output profile provided at a previous process step, a target profile and process condition information of a current process step; and generating, at the first process emulation cell, a current output profile corresponding to the current process step, based on the target profile, the process condition information, and prior knowledge information, the prior knowledge information defining a time series causal relationship between the previous process step and the current process step.