公开(公告)号：US20180158871A1

公开(公告)日：2018-06-07

申请号：US15653198

申请日：2017-07-18

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/24 ,  H01L27/22 ,  H01L27/108

CPC classification number: H01L27/10894 ,  H01L27/10823 ,  H01L27/10844 ,  H01L27/10876 ,  H01L27/10897 ,  H01L27/228 ,  H01L27/2436

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20240365535A1

公开(公告)日：2024-10-31

申请号：US18397014

申请日：2023-12-27

Applicant: SAMSUNG ELECTRONICS CO, LTD.

Inventor： Jongmin KIM ,  Kiseok LEE ,  Bongsoo KIM ,  Chan-Sic YOON

IPC: H10B12/00

CPC classification number: H10B12/488 ,  H10B12/315 ,  H10B12/482 ,  H10B12/485

Abstract: A semiconductor device includes a first active pattern including a first edge portion and a second edge portion, which are spaced apart from each other in a first direction; a first word line between the first edge portion of the first active pattern and the second edge portion of the first active pattern and extending in a second direction that crosses the first direction; a bit line on the first edge portion of the first active pattern and extending in a third direction that crosses the first direction and the second direction; and a storage node contact on the second edge portion of the first active pattern, wherein a top surface of the first edge portion is at a level higher than a top surface of the second edge portion.

公开(公告)号：US20240268102A1

公开(公告)日：2024-08-08

申请号：US18471583

申请日：2023-09-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Kiseok LEE ,  Seung-Bo KO ,  Jongmin KIM ,  Hui-Jung KIM ,  SangJae PARK ,  Taejin PARK ,  Chan-Sic YOON ,  Myeong-Dong LEE ,  Hongjun LEE ,  Minju KANG ,  Keunnam KIM

IPC: H10B12/00

CPC classification number: H10B12/485 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor device includes first and second active patterns extending in a first direction and arranged in a second direction intersecting the first direction, each of the first and second active patterns including first and second edge portions spaced apart from each other in the first direction, a first storage node pad and a first storage node contact sequentially provided on the first edge portion of the first active pattern, and a second storage node pad and a second storage node contact sequentially provided on the second edge portion of the second active pattern. Each of the first and second storage node contacts includes a metal material.

公开(公告)号：US20240064964A1

公开(公告)日：2024-02-22

申请号：US18191291

申请日：2023-03-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jong Min KIM ,  Chan-Sic YOON ,  Jun Hyeok AHN

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/485 ,  H10B12/482 ,  H10B12/488

Abstract: Provided is a semiconductor memory device. The semiconductor memory device includes a substrate including an active region defined by a device isolation layer, a bit line which is disposed on the substrate and extends in a first direction, a bit line contact which is disposed between the bit line and the substrate and connects the bit line to the active region, a bit line spacer which extends along a sidewall of the bit line, and a bit line contact spacer which extends along a sidewall of the bit line contact and does not extend along the sidewall of the bit line.

公开(公告)号：US20230071440A1

公开(公告)日：2023-03-09

申请号：US17737115

申请日：2022-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ah Rang CHOI ,  Chan-Sic YOON ,  Jung-Hoon HAN ,  Gyu Hyun KIL ,  Weon Hong KIM ,  Doo San BACK

IPC: H01L27/108

Abstract: Inventive concepts relate to a semiconductor memory device. The semiconductor memory device comprising, a substrate comprising an NMOS region and a PMOS region, a first gate pattern the NMOS region of the substrate, and a second gate pattern disposed on the PMOS region of the substrate. The first gate pattern comprises a first high-k layer, a diffusion mitigation pattern, an N-type work function pattern, and a first gate electrode, which are sequentially stacked on the substrate, the second gate pattern comprises a second high-k layer and a second gate electrode which are sequentially stacked on the substrate, the diffusion mitigation pattern is in contact with the first high-k layer, a stacked structure of the first gate electrode is the same as that of the second gate electrode, and the second gate pattern does not comprise the N-type work function pattern.

公开(公告)号：US20210408008A1

公开(公告)日：2021-12-30

申请号：US17471824

申请日：2021-09-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Kiseok LEE ,  Chan-Sic YOON ,  Augustin HONG ,  Keunnam KIM ,  Dongoh KIM ,  Bong-Soo KIM ,  Jemin PARK ,  Hoin LEE ,  Sungho JANG ,  Kiwook JUNG ,  Yoosang HWANG

IPC: H01L27/108 ,  H01L27/24

Abstract: A method of manufacturing a semiconductor memory device and a semiconductor memory device, the method including providing a substrate that includes a cell array region and a peripheral circuit region; forming a mask pattern that covers the cell array region and exposes the peripheral circuit region; growing a semiconductor layer on the peripheral circuit region exposed by the mask pattern such that the semiconductor layer has a different lattice constant from the substrate; forming a buffer layer that covers the cell array region and exposes the semiconductor layer; forming a conductive layer that covers the buffer layer and the semiconductor layer; and patterning the conductive layer to form conductive lines on the cell array region and to form a gate electrode on the peripheral circuit region.

公开(公告)号：US20180233506A1

公开(公告)日：2018-08-16

申请号：US15954744

申请日：2018-04-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Chan-Sic YOON ,  Ho-In RYU ,  Ki-Seok LEE ,  Chang-Hyun CHO

IPC: H01L27/108 ,  H01L29/423 ,  H01L21/311 ,  H01L21/761

CPC classification number: H01L27/10876 ,  H01L21/31111 ,  H01L21/761 ,  H01L27/10814 ,  H01L27/10855 ,  H01L27/10891 ,  H01L29/4236

Abstract: A semiconductor device includes a substrate having an active region defined by a device isolation layer and at least a gate trench linearly extending in a first direction to cross the active region, the active region having a gate area at a bottom of the gate trench and a junction area at a surface of the substrate. The device further may include a first conductive line filling the gate trench and extending in the first direction, the first conductive line having a buried gate structure on the gate area of the active region. The device also may include a junction including implanted dopants at the junction area of the active region, and a junction separator on the device isolation layer and defining the junction. The junction separator may be formed of an insulative material and have an etch resistance greater than that of the device isolation layer.