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    SEMICONDUCTOR MEMORY DEVICE
    11.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20230320076A1

    公开(公告)日：2023-10-05

    申请号：US17983489

    申请日：2022-11-09

    Applicant: Samsung Electronics Co., LTD.

    Inventor： HYO-SUB KIM ,  Kseok LEE ,  Myeong-Dong LEE ,  Jongmin KIM ,  Hui-Jung KIM ,  Jihun LEE ,  Hongjun LEE

    IPC: H01L27/108 ,  G11C5/06

    CPC classification number: H01L27/10814 ,  G11C5/063

    Abstract: A semiconductor memory device includes: a device isolation pattern provided on a substrate to provide a first active portion and a second active portion; a first storage node pad disposed on the first active portion; a second storage node pad disposed on the second active portion; a pad separation pattern disposed between the first and second storage node pads; a word line disposed in the substrate to cross the first and second active portions; a bit line disposed on the pad separation pattern and crossing the word line; a buffer layer disposed on the pad separation pattern; and a mask polysilicon pattern interposed between the buffer layer and the bit line, wherein a side surface of the mask polysilicon pattern is substantially aligned to a side surface of the bit line, and the mask polysilicon pattern is vertically overlapped with the pad separation pattern.

    SEMICONDUCTOR DEVICE HAVING LANDING PAD STRUCTURE
    13.
    发明申请
    SEMICONDUCTOR DEVICE HAVING LANDING PAD STRUCTURE 有权

    公开(公告)号：US20250040123A1

    公开(公告)日：2025-01-30

    申请号：US18665984

    申请日：2024-05-16

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin KIM ,  Seungbo KO ,  Kiseok LEE

    IPC: H10B12/00

    Abstract: A semiconductor device includes a substrate having an active region, a gate structure on the substrate, the gate structure extending across the active region in a first horizontal direction, bit line structures on bit line trenches extending in a second horizontal direction, intersecting the first horizontal direction, the bit line trenches on an upper surface of the substrate across the gate structure, contact plugs between the bit line structures, landing pad structures on the contact plugs, and an insulating pattern between the landing pad structures, the insulating pattern in contact with the bit line structures. Portions of the bit line structures extend in the second horizontal direction in the bit line trenches. Each of the landing pad structures includes a lower landing pad, arranged on a level lower than that of each of upper surfaces of the bit line structures, and an upper landing pad on the lower landing pad.

    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME
    14.
    发明申请
    SEMICONDUCTOR DEVICE AND METHOD OF FABRICATING THE SAME 有权

    公开(公告)号：US20250031363A1

    公开(公告)日：2025-01-23

    申请号：US18413813

    申请日：2024-01-16

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Minju KANG ,  Jongmin KIM ,  Sangjae PARK ,  Sohyun PARK ,  Kiseok LEE

    IPC: H10B12/00 ,  H10N50/80 ,  H10N70/00

    Abstract: A semiconductor device includes a first active pattern including a first edge portion and a second edge portion spaced apart from the first edge portion in a first direction, a first word line between the first edge portion and the second edge portion and extending in a second direction intersecting the first direction, a bit line on the first edge portion and extending in a third direction intersecting the first direction and the second direction, and a storage node contact on the second edge portion, where the first edge portion includes a first top surface and a second top surface, and the second top surface of the first edge portion is closer to the second edge portion than the first top surface of the first edge portion.

    STORAGE CONTROLLER AND OPERATING METHOD OF THE STORAGE CONTROLLER
    15.
    发明公开
    STORAGE CONTROLLER AND OPERATING METHOD OF THE STORAGE CONTROLLER 审中-公开

    公开(公告)号：US20240311304A1

    公开(公告)日：2024-09-19

    申请号：US18502233

    申请日：2023-11-06

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Minsik OH ,  Donggil KANG ,  Kyungjune CHO ,  Jongmin KIM ,  Jinwoo SONG ,  Kyungsik UM ,  Myunggwan JEONG

    IPC: G06F12/0815 ,  G06F12/0862

    CPC classification number: G06F12/0815 ,  G06F12/0862

    Abstract: A storage controller includes a host interface configured to communicate with a host, a buffer memory configured to buffer data read from a non-volatile memory, a cache memory including a plurality of cache lines and configured to store the data in at least one of the plurality of cache lines, and a cache controller configured to manage a status bitmap. The status bitmap indicates priority information of the plurality of cache lines according to an operation corresponding to a request received from the host interface, and the cache controller is further configured to select a victim cache line, among the plurality of cache lines, to be replaced based on the status bitmap. In this case, the operation corresponding to the request corresponds to one of normal read, prefetch, read-after-read, and read-after-prefetch.

    SEMICONDUCTOR DEVICE
    16.
    发明公开
    SEMICONDUCTOR DEVICE 审中-公开

    公开(公告)号：US20240147710A1

    公开(公告)日：2024-05-02

    申请号：US18457756

    申请日：2023-08-29

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jongmin KIM ,  Chansic YOON

    IPC: H10B12/00

    CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315

    Abstract: A semiconductor device may include a substrate including a cell region and a connection region, a cell word line extending across the plurality of active regions in a first horizontal direction on the cell region of the substrate, a cell bit line including a cell metallic conductive pattern extending on the cell region of the substrate in a second horizontal direction, and a connection bit line including a connection metallic conductive pattern extending in the second horizontal direction on the connection region of the substrate. A top surface of the connection bit line may be located at a vertical level that is equal to or lower than a top surface of the cell bit line, and a height of the connection metallic conductive pattern in a vertical direction may be equal to or greater than a height of the cell metallic conductive pattern in the vertical direction.

    SEMICONDUCTOR MEMORY DEVICE
    17.
    发明公开
    SEMICONDUCTOR MEMORY DEVICE 审中-公开

    公开(公告)号：US20240130118A1

    公开(公告)日：2024-04-18

    申请号：US18138495

    申请日：2023-04-24

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Jongmin KIM ,  Chansic YOON

    IPC: H10B12/00

    CPC classification number: H10B12/50 ,  H10B12/09 ,  H10B12/315 ,  H10B12/34 ,  H10B12/482

    Abstract: A semiconductor memory device is provided. The semiconductor memory device includes: a substrate including a plurality of active regions in a memory cell region and at least one logic active region in a peripheral circuit region; a word line extending in a first horizontal direction on the plurality of active regions; a bit line structure extending in a second horizontal direction orthogonal to the first horizontal direction, on the plurality of active regions, and including a bit line, a cover insulating structure on a side surface of an end of the bit line, and an insulating capping structure on the bit line and the cover insulating structure; and a gate line on the at least one logic active region

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