Flexible display
    12.
    发明授权

    公开(公告)号:US12178095B2

    公开(公告)日:2024-12-24

    申请号:US18209556

    申请日:2023-06-14

    Abstract: A flexible display is disclosed. In one aspect, the display includes at least one first pattern including a plurality of display elements configured to display an image and extending in a first direction. The display device also includes at least one second pattern extending in a second direction and overlapping at least a portion of the first pattern. The second pattern has a curved shape in the first direction and the second direction crosses the first direction. The first and second patterns form at least one cavity region defining a space therebetween and the first and second patterns form a mesh structure.

    Gate driving circuit and display device including the same

    公开(公告)号:US10733950B2

    公开(公告)日:2020-08-04

    申请号:US16518710

    申请日:2019-07-22

    Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k−1)th carry signal from a (k−1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.

    Gate driving circuit and display device including the same

    公开(公告)号:US10360863B2

    公开(公告)日:2019-07-23

    申请号:US15227924

    申请日:2016-08-03

    Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k−1)th carry signal from a (k−1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.

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