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公开(公告)号:US09734785B2
公开(公告)日:2017-08-15
申请号:US14821329
申请日:2015-08-07
Applicant: Samsung Display Co., LTD.
Inventor: Sehyoung Cho , Kyung-hoon Kim , Dongwoo Kim , Ilgon Kim , Meehye Jung , Kangmoon Jo
IPC: G09G3/36 , G09G3/3266 , H03K17/56
CPC classification number: G09G3/3677 , G09G3/3266 , G09G2300/0413 , G09G2300/0426 , G09G2310/0267 , G09G2310/0286 , G09G2330/08 , H03K17/56
Abstract: Provided is a gate driving unit including: a plurality of stages configured to be activated sequentially so as to generate gate signals; and a plurality of repair blocks having sizes smaller than the corresponding stages and configured to repair defects of the stages. Each of the repair blocks is disposed proximate to two or more stages so as to be configured to repair defects in the two or more stages.
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公开(公告)号:US12178095B2
公开(公告)日:2024-12-24
申请号:US18209556
申请日:2023-06-14
Applicant: SAMSUNG DISPLAY CO., LTD.
Inventor: Gyungsoon Park , Minjae Jeong , Keumnam Kim , Sehyoung Cho , Jongho Hong
IPC: H10K59/131 , G09G3/00 , G09G3/20 , H10K77/10 , H10K102/00
Abstract: A flexible display is disclosed. In one aspect, the display includes at least one first pattern including a plurality of display elements configured to display an image and extending in a first direction. The display device also includes at least one second pattern extending in a second direction and overlapping at least a portion of the first pattern. The second pattern has a curved shape in the first direction and the second direction crosses the first direction. The first and second patterns form at least one cavity region defining a space therebetween and the first and second patterns form a mesh structure.
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公开(公告)号:US10733950B2
公开(公告)日:2020-08-04
申请号:US16518710
申请日:2019-07-22
Applicant: Samsung Display Co., Ltd.
Inventor: Junghwan Hwang , Sehyoung Cho
IPC: G09G3/36
Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k−1)th carry signal from a (k−1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.
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公开(公告)号:US10360863B2
公开(公告)日:2019-07-23
申请号:US15227924
申请日:2016-08-03
Applicant: Samsung Display Co., Ltd.
Inventor: Junghwan Hwang , Sehyoung Cho
IPC: G09G3/36
Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k−1)th carry signal from a (k−1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.
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公开(公告)号:US09899429B2
公开(公告)日:2018-02-20
申请号:US15272140
申请日:2016-09-21
Applicant: Samsung Display Co., Ltd.
Inventor: Jangmi Kang , Meehye Jung , Hyunjoon Kim , Cheolgon Lee , Sehyoung Cho , Injae Hwang
CPC classification number: H01L27/1244 , H01L24/05 , H01L27/127 , H01L27/3223 , H01L27/3262 , H01L27/3276 , H01L29/78666 , H01L29/78675 , H01L51/0541 , H01L2224/02251 , H01L2224/02255 , H01L2224/06135 , H01L2224/06155 , H01L2227/323 , H01L2251/5392 , H01L2924/381
Abstract: A display device includes a substrate including a display region, and a peripheral region that is outside of the display region, a plurality of dummy pads at the peripheral region, an insulating layer covering the plurality of dummy pads, wherein top surfaces of first portions of the insulating layer above the plurality of dummy pads are higher than top surfaces of second portions of the insulating layer between the plurality of dummy pads, and a plurality of pads over the second portions of the insulating layer at the peripheral region.
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