公开(公告)号：US11037517B2

公开(公告)日：2021-06-15

申请号：US16666054

申请日：2019-10-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junghwan Hwang ,  Chanwook Shim ,  Youngchul Jo

IPC: G09G3/36

Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.

公开(公告)号：US12148391B2

公开(公告)日：2024-11-19

申请号：US18103260

申请日：2023-01-30

Applicant: Samsung Display Co., Ltd.

Inventor： Yanghwa Choi ,  Junghwan Hwang

IPC: G09G3/3266 ,  G09G3/3258

Abstract: An embodiment of a display apparatus includes a scan driver, a pixel, a first scan line electrically connecting the scan driver to the pixel, a second scan line electrically connecting the scan driver to the pixel, and a third scan line electrically connecting the scan driver to the pixel, wherein in operation: the pixel receives first, second, and third scan signals from the scan driver by way of the first, second, and third scan lines, respectively; the first and second scan signals produce a display period of a frame period in the pixel; and the third scan signal produces a black insertion period of the frame period in the pixel.

公开(公告)号：US20230113452A1

公开(公告)日：2023-04-13

申请号：US17657256

申请日：2022-03-30

Applicant: Samsung Display Co., Ltd.

Inventor： Hyuk Kim ,  Yanghwa Choi ,  Junghwan Hwang

IPC: G09G3/3266 ,  G09G3/3233

Abstract: A display apparatus includes: a pixel part including a plurality of pixels, each of the plurality of pixels to receive a first scan signal and an emission signal; and a scan driver to output the first scan signal and the emission signal to each of the plurality of pixels. In a second driving mode in which the display apparatus is driven with a first driving frequency lower than a maximum driving frequency, the scan driver is to supply the first scan signal to the plurality of pixels according to the first driving frequency, and supply the emission signal to the plurality of pixels according to the maximum driving frequency.

公开(公告)号：US11568822B2

公开(公告)日：2023-01-31

申请号：US17377293

申请日：2021-07-15

Applicant: Samsung Display Co., Ltd.

Inventor： Yanghwa Choi ,  Junghwan Hwang

IPC: G09G3/3266 ,  G09G3/3258

Abstract: An embodiment of a display apparatus includes a scan driver, a pixel, a first scan line electrically connecting the scan driver to the pixel, a second scan line electrically connecting the scan driver to the pixel, and a third scan line electrically connecting the scan driver to the pixel, wherein in operation: the pixel receives first, second, and third scan signals from the scan driver by way of the first, second, and third scan lines, respectively; the first and second scan signals produce a display period of a frame period in the pixel; and the third scan signal produces a black insertion period of the frame period in the pixel.

公开(公告)号：US11568776B2

公开(公告)日：2023-01-31

申请号：US17143207

申请日：2021-01-07

Applicant: Samsung Display Co., Ltd.

Inventor： Junghwan Hwang

IPC: G09G3/20

Abstract: A gate driver includes a plurality of active stages and a plurality of dummy stages. The active stage is configured to output a plurality of gate signals to a display region. The dummy stage is c connected to respective active stages and configured to output a plurality of dummy carry signals to the respective active stages. The active stage is configured to output the plurality of gate signals and a plurality of active carry signals. The plurality of dummy stages are configured to output the plurality of dummy carry signals, respectively, and not to output any gate signal.

公开(公告)号：US11557257B2

公开(公告)日：2023-01-17

申请号：US17572938

申请日：2022-01-11

Applicant: Samsung Display Co., Ltd.

Inventor： Junghwan Hwang ,  Yang-Hwa Choi

IPC: G09G3/3266 ,  G09G3/3291

Abstract: A pixel includes a first transistor, a second transistor, a third transistor, a capacitor, and a light emitting diode. During a non-emission period of a low frequency mode, the third transistor electrically connects a first terminal of the light emitting diode to an initialization voltage line in response to a second scan signal. An initialization voltage transferred from the initialization voltage line has a first voltage level during a normal mode different from the low frequency mode, and has a second voltage level different from the first voltage level during the non-emission period of the low frequency mode.

公开(公告)号：US20170110076A1

公开(公告)日：2017-04-20

申请号：US15227924

申请日：2016-08-03

Applicant: Samsung Display Co., Ltd.

Inventor： Junghwan Hwang ,  Sehyoung Cho

IPC: G09G3/36

CPC classification number: G09G3/3677 ,  G09G3/3648 ,  G09G3/3696 ,  G09G2310/0286

Abstract: A gate driving circuit includes: a plurality of stages to provide gate signals to gate lines of a display panel, a k-th stage, where k is a natural number greater than or equal to 2, from among the plurality of stages being configured: to receive a clock signal, a (k−1)th carry signal from a (k−1)th stage, a (k+1)th carry signal from a (k+1)th stage, a (k+2)th carry signal from a (k+2)th stage, a first voltage, and a second voltage, the clock signal being a pulse signal in which a high voltage and a third voltage appear periodically, and the third voltage having a lower voltage level than those of the first voltage and the second voltage; and to output a k-th gate signal and a k-th carry signal.

公开(公告)号：US12190823B2

公开(公告)日：2025-01-07

申请号：US18103260

申请日：2023-01-30

Applicant: Samsung Display Co., Ltd.

Inventor： Yanghwa Choi ,  Junghwan Hwang

IPC: G09G3/3266 ,  G09G3/3258

Abstract: An embodiment of a display apparatus includes a scan driver, a pixel, a first scan line electrically connecting the scan driver to the pixel, a second scan line electrically connecting the scan driver to the pixel, and a third scan line electrically connecting the scan driver to the pixel, wherein in operation: the pixel receives first, second, and third scan signals from the scan driver by way of the first, second, and third scan lines, respectively; the first and second scan signals produce a display period of a frame period in the pixel; and the third scan signal produces a black insertion period of the frame period in the pixel.

公开(公告)号：US12027090B2

公开(公告)日：2024-07-02

申请号：US18092402

申请日：2023-01-02

Applicant: Samsung Display Co., Ltd.

Inventor： Junghwan Hwang

IPC: G09G5/00 ,  G09G3/20

CPC classification number: G09G3/20 ,  G09G2300/0413 ,  G09G2310/0275 ,  G09G2310/08

Abstract: A gate driver includes a plurality of active stages and a plurality of dummy stages. The active stage is configured to output a plurality of gate signals to a display region. The dummy stage is c connected to respective active stages and configured to output a plurality of dummy carry signals to the respective active stages. The active stage is configured to output the plurality of gate signals and a plurality of active carry signals. The plurality of dummy stages are configured to output the plurality of dummy carry signals, respectively, and not to output any gate signal.

公开(公告)号：US11727851B2

公开(公告)日：2023-08-15

申请号：US17703420

申请日：2022-03-24

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junghwan Hwang ,  Doo-young Lee

IPC: G09G3/3266 ,  G09G3/3225 ,  G09G3/20

CPC classification number: G09G3/2092 ,  G09G2300/0426 ,  G09G2310/0275

Abstract: A gate driver includes active stages that output gate signals to a display part and pre-stages connected to the active stages to output carry signals to the active stages. The pre-stages include a first pre-stage and a second pre-stage. The second pre-stage includes a Q node compensator that receives a clock signal from the first pre-stage and compensates for a voltage of a Q node based on the clock signal of the first pre-stage. The Q node compensator includes a feedback transistor that diode-connects a feedback input terminal, which receives the clock signal of the first pre-stage, to a feedback node of the second pre-stage. The feedback transistor includes a first electrode, a second electrode, and a third electrode, where the first electrode is connected to the feedback input terminal, the second electrode is connected to the first electrode, and the third electrode is connected to the feedback node.