公开(公告)号：US10529292B2

公开(公告)日：2020-01-07

申请号：US15497354

申请日：2017-04-26

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Chanwook Shim

IPC: G09G3/36

Abstract: A method of driving a display panel and a display apparatus having a plurality of gate lines and a plurality of data lines that cross the gate lines. The method includes determining whether to compensate a gate signal or not according to input image data displayed on a display panel, transmitting a first gate signal having a first falling waveform to a first gate line and a second gate signal having a second falling waveform different from the first falling waveform to the second gate line. A first gate clock signal may be adjusted when the gate signal is determined to be compensated. A timing controller may compensate the first gate signal when an artifact would be displayed based on a variation in brightness when a first subpixel row to which the first gate signal is applied is brighter than a second subpixel row for a same target luminance.

公开(公告)号：US11037517B2

公开(公告)日：2021-06-15

申请号：US16666054

申请日：2019-10-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junghwan Hwang ,  Chanwook Shim ,  Youngchul Jo

IPC: G09G3/36

Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.

公开(公告)号：US10460691B2

公开(公告)日：2019-10-29

申请号：US15162499

申请日：2016-05-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junghwan Hwang ,  Chanwook Shim ,  Youngchul Jo

IPC: G09G3/36

Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.

公开(公告)号：US20200066224A1

公开(公告)日：2020-02-27

申请号：US16666054

申请日：2019-10-28

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junghwan Hwang ,  Chanwook Shim ,  Youngchul Jo

IPC: G09G3/36

Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.

公开(公告)号：US20170084245A1

公开(公告)日：2017-03-23

申请号：US15162499

申请日：2016-05-23

Applicant: SAMSUNG DISPLAY CO., LTD.

Inventor： Junghwan Hwang ,  Chanwook Shim ,  Youngchul Jo

IPC: G09G3/36

Abstract: A display device to display an image during frame intervals, and to display a blank image during a blank interval defined between the frame intervals, includes: a gate driving circuit including a plurality of stages, an ith stage (i is an integer greater than or equal to 2) from among the plurality of stages including a clock terminal to receive a clock signal, wherein the clock signal swings between a first clock voltage and a second clock voltage smaller than the first clock voltage during a normal interval corresponding to each of the frame intervals, and the clock signal is changed to a voltage lower than the second clock voltage during a stabilization interval corresponding to the blank interval.