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公开(公告)号：US10484165B2
公开(公告)日：2019-11-19
申请号：US15846560
申请日：2017-12-19
发明人： Rupesh Singh , Ankur Bal
IPC分类号： H04L7/00
摘要： Data words are received in parallel in response to an edge of a master clock signal and selected for serial output in response to a select signal. For a detected temporal offset of the serially output data words, the generation of the select signal and the master clock signal are controlled to correct for the temporal offset by shifting timing of the edge of the master clock signal and adjusting a sequence of values for the select signal that are generated within one cycle of the master clock signal. For a backward temporal offset, at least one count value in the sequence of values is skipped and the edge of the master clock signal occurs earlier in time. For a forward temporal offset, at least one count value in the sequence of values is held and the edge of the master clock signal occurs later in time.
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公开(公告)号：US11563443B2
公开(公告)日：2023-01-24
申请号：US17374351
申请日：2021-07-13
发明人： Ankur Bal , Rupesh Singh
摘要： A latch circuit sequentially latches a first data weighted averaging (DWA) data word and then a second DWA data word. A first detector circuit identifies a first bit location in the first DWA data that is associated with an ending of a first string of logic 1 bits in the first DWA data word. A second detector circuit identifies a second bit location in the second DWA data word associated with an ending of a second string of logic 1 bits in the second DWA data word. A DWA-to-binary conversion circuit converts the second DWA data word to a binary word by using the first bit location and second bit location to identify a number of logic 1 bits present in said second DWA data word. A binary value for that binary word that is equal to the identified number is output.
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公开(公告)号：US11411565B2
公开(公告)日：2022-08-09
申请号：US17131917
申请日：2020-12-23
发明人： Rupesh Singh , Ankur Bal
摘要： A first sampling circuit takes phase offset first samples of a received serial data stream in response to a first edge of a sampling clock and a first comparator circuit determines whether the plurality of phase offset first samples have a same logic state. A second sampling circuit takes phase offset second samples of the received serial data stream in response to a second edge of the sampling clock, opposite the first edge, and a second comparator circuit determines whether the phase offset second samples have a same logic state. One of the first samples or one of the second samples is then selected in response to the determinations made by the first and second comparator circuits. A serial to parallel converter circuit generates an output word including the selected one of the first and second samples.
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公开(公告)号：US11043960B2
公开(公告)日：2021-06-22
申请号：US16895183
申请日：2020-06-08
发明人： Ankur Bal , Rupesh Singh
摘要： A sigma-delta modulator includes an N-bit quantization circuit that generates a stream of N-bit code words and a feedback signal path with an N-bit DAC circuit, having a non-ideal operation due to mismatch error, that converts the stream of N-bit code words to generate a feedback signal. A digital DAC copy circuit provides a digital replication of the N-bit DAC circuit. The digital replication accounts for the non-ideal operation of the N-bit DAC circuit 126 due to mismatch error, and converts the stream of N-bit code words to generate a stream of P-bit code words, where P>N, that are functionally equivalent to the feedback signal output from the N-bit DAC circuit.
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15.发明授权公开(公告)号：US10862503B2
公开(公告)日：2020-12-08
申请号：US16702246
申请日：2019-12-03
发明人： Ankur Bal , Rupesh Singh
摘要： A continuous time Delta-Sigma (CT-ΔΣ) modulator has an input node configured to receive an input signal and an output node configured to output a digital output signal. The CT-ΔΣ modulator includes a feedback loop with a summation circuit configured to sum the digital output signal with a jitter perturbed test signal to generate a signal supplied to an input of a digital to analog converter circuit. A single tone signal is injected with a jitter error of a clock signal to generate the jitter perturbed test signal. A processing circuit processes the digital output signal to detect a signal to noise ratio of the CT-ΔΣ modulator. The detected signal to noise ratio is indicative of presence of jitter in the clock signal.
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公开(公告)号：US10211850B1
公开(公告)日：2019-02-19
申请号：US16034467
申请日：2018-07-13
发明人： Ankur Bal , Rupesh Singh
摘要： Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.
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公开(公告)号：US10050640B1
公开(公告)日：2018-08-14
申请号：US15864233
申请日：2018-01-08
发明人： Ankur Bal , Rupesh Singh
摘要： Data weighted averaging of a thermometric coded input signal is accomplished by controlling the operation of a crossbar switch matrix to generate a current cycle of a data weighted averaging output signal using a control signal generated in response to feedback of a previous cycle of the data weighted averaging output signal. The control signal specifies a bit location for a beginning logic transition of the data weighted averaging output signal in the current cycle based on detection of an ending logic transition of the data weighted averaging output signal in the previous cycle.
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