公开(公告)号：US20240429174A1

公开(公告)日：2024-12-26

申请号：US18750274

申请日：2024-06-21

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Kwangbae KIM ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/538 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31 ,  H01L25/18 ,  H10B80/00

Abstract: A semiconductor package according to an embodiment includes a first semiconductor chip, a second semiconductor chip, a first dielectric film surrounding the first semiconductor chip and the second semiconductor chip; first vias; second vias; a bridge chip; a second dielectric film surrounding the bridge chip and having an upper surface and a lower surface opposite to the upper surface; and a third via, some of the first vias are electrically connected to some of the bridge chip pads, some of the second vias are electrically connected to others of the bridge chip pads, and the passivation layer includes a same material as a material of the first dielectric film.

公开(公告)号：US20240088006A1

公开(公告)日：2024-03-14

申请号：US18317521

申请日：2023-05-15

Applicant: Samsung Electronics Co., Ltd.

Inventor： Sangcheon PARK ,  Dongwoo KANG ,  Unbyoung KANG ,  Soohwan LEE ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/498 ,  H01L23/00 ,  H01L23/538

CPC classification number: H01L23/49827 ,  H01L23/5389 ,  H01L24/06 ,  H01L24/32 ,  H01L2224/0401 ,  H01L2224/06515 ,  H01L2224/32235 ,  H01L2924/1434

Abstract: Provided is a semiconductor package including a substrate including a first surface and a second surface opposite to the first surface, a connecting circuit arranged on the first surface of the substrate, a through silicon via (TSV) structure penetrating the substrate, a first passivation layer arranged on the connecting circuit, a second passivation layer arranged on the second surface, a first bumping pad arranged inside the first passivation layer, and a second bumping pad arranged inside the second passivation layer, wherein the first bumping pad includes a first pad plug, and a first seed layer surrounding a lower surface and sidewalls of the first pad plug, wherein the second bumping pad includes a second pad plug, and a second seed layer surrounding an upper surface and sidewalls of the second pad plug, and wherein the first seed layer and the second seed layer include materials having different reactivities to water.

公开(公告)号：US20250167178A1

公开(公告)日：2025-05-22

申请号：US19029370

申请日：2025-01-17

Applicant: Samsung Electronics Co., Ltd.

Inventor： Youngkun JEE ,  Unbyoung KANG ,  Sanghoon LEE ,  Chungsun LEE

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

公开(公告)号：US20250096066A1

公开(公告)日：2025-03-20

申请号：US18882385

申请日：2024-09-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/367 ,  H01L21/48 ,  H01L21/56 ,  H01L23/00 ,  H01L23/373 ,  H01L25/18 ,  H05K1/18 ,  H10B80/00

Abstract: Provided is a semiconductor package, including a first redistribution structure, a first chip on the first redistribution structure, a molding member on the first redistribution structure and surrounding the first chip, a conductive pillar penetrating through the molding member in a first direction, a second redistribution structure on a second surface of the molding member, a second chip on the second redistribution structure, and a heat dissipation chip at least partially overlapping the first chip in the vertical direction, wherein the second redistribution structure at least partially overlaps the heat dissipation chip in a second direction intersecting the first direction.

公开(公告)号：US20250087624A1

公开(公告)日：2025-03-13

申请号：US18611241

申请日：2024-03-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Sungjin Han ,  Gyeongjae JO ,  Hyunchul JUNG ,  Youngkun JEE

IPC: H01L23/00

Abstract: A semiconductor package manufacturing apparatus is provided and includes a bonding head including at least one vacuum hole, and at least one adsorption trench in a lower surface of the bonding head and connected to the at least one vacuum hole. A lower part of the bonding head includes at least one first portion, and a second portion spaced apart from the at least one first portion and surrounding the at least one first portion in a plan view. The at least one adsorption trench is defined by and between the at least one first portion and the second portion, and at least a portion of an inner surface of the at least one adsorption trench and at least a portion of an outer surface of the at least one adsorption trench are curved in the plan view.

公开(公告)号：US20250015042A1

公开(公告)日：2025-01-09

申请号：US18751869

申请日：2024-06-24

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jing Cheng LIN ,  Youngkun JEE

IPC: H01L23/00 ,  H01L21/56 ,  H01L23/498

Abstract: A method of manufacturing a semiconductor package is provided. The method includes: forming a plurality of sacrificial pads on a carrier substrate and a plurality of sacrificial solder bumps on the plurality of sacrificial pads, respectively; forming a plurality of conductive pillars and a protective insulating layer on a semiconductor chip, the protective insulating layer surrounding a side surface of each of the plurality of conductive pillars; polishing the plurality of conductive pillars and the protective insulating layer to obtain a polished surface in which a surface of each of the plurality of conductive pillars is coplanar with a surface of the protective insulating layer; and bonding the plurality of conductive pillars to the plurality of sacrificial solder bumps, respectively.

公开(公告)号：US20240395764A1

公开(公告)日：2024-11-28

申请号：US18624233

申请日：2024-04-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Gyeongjae JO ,  Sangcheon PARK ,  Youngkun JEE

IPC: H01L23/00

Abstract: A bonding apparatus for a semiconductor device including: a substrate state having a seating surface on which a first semiconductor device is placed; a head portion having a lower surface, the head portion configured to hold a second semiconductor device on the lower surface to face the first semiconductor device, the lower surface including a first portion having a first height from the seating surface and a second portion having a second height from the seating surface, the second height being greater than the first height, the lower surface being inclined at an angle with respect to the seating surface; and a transfer portion provided on the head portion to move the head portion, the transfer portion configured to press the head portion from the first portion to the second portion such that the first and second semiconductor devices are bonded to each other.