公开(公告)号：US20230400972A1

公开(公告)日：2023-12-14

申请号：US18131728

申请日：2023-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjin HAN ,  Yonghwan Kwon ,  Hyeonji Lee ,  Seokhyun Kim ,  Junggeun Kim ,  Hyunsoo Yuk

IPC: G06F3/04845 ,  G06F3/0362 ,  G06F3/0354

CPC classification number: G06F3/04845 ,  G06F3/03547 ,  G06F3/03543 ,  G06F3/0362

Abstract: An electronic device includes a display and a processor configured to control the display to display a user interface (UI) screen including a plurality of graphical user interface (GUI) items and a focus GUI, identify, based on a wheel input of a user, arrangement information about the plurality of GUI items, identify, based on the arrangement information, a possible movement direction of the focus GUI displayed at a location corresponding to one GUI item among the plurality of GUI items, based on the identified possible movement direction of the focus GUI including both a horizontal direction and a vertical direction, identify a movement direction of the focus GUI as the horizontal direction, and control the display to move the focus GUI based on a manipulation direction of the wheel input and the identified movement direction.

公开(公告)号：US11735571B2

公开(公告)日：2023-08-22

申请号：US17321906

申请日：2021-05-17

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon

IPC: H01L23/495 ,  H01L25/10 ,  H01L23/538 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/49838 ,  H01L23/5383 ,  H01L23/5389 ,  H01L2225/1023 ,  H01L2225/1041 ,  H01L2225/1058

Abstract: A semiconductor package includes: a first wiring pattern; a dielectric layer that covers the first wiring pattern; a second wiring pattern on the dielectric layer, wherein the second wiring pattern includes a line part that extends in a first direction and a via part that connects the line part to the first wiring pattern; a pad pattern electrically connected to the second wiring pattern, wherein the pad pattern includes a connection part and an extension part, wherein the connection part covers a first surface of the line part of the second wiring pattern, and the extension part has a top surface at a level lower than a level of the top surface of the line part of the second wiring pattern; and a seed pattern between the extension part and the dielectric layer.

公开(公告)号：US11569137B2

公开(公告)日：2023-01-31

申请号：US17245628

申请日：2021-04-30

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon

IPC: H01L21/66 ,  H01L23/538 ,  H01L23/00 ,  H01L21/683 ,  H01L21/48 ,  H01L21/56 ,  H01L23/31

Abstract: A semiconductor package includes a semiconductor chip having first and second contact pads that are alternately arranged in a first direction; an insulating film having first openings respectively defining first pad regions of first contact pads, and second openings respectively defining second pad regions of the second contact pads; first and second conductive capping layers on the first and second pad regions, respectively; and an insulating layer on the insulating film, and having first and second contact holes respectively connected to the first and second conductive capping layers. Each of the first and second pad regions includes a bonding region having a first width and a probing region having a second width, greater than the first width, and each of the second pad regions is arranged in a direction that is opposite to each of the plurality of first pad regions.

公开(公告)号：USD936089S1

公开(公告)日：2021-11-16

申请号：US29736638

申请日：2020-06-02

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Designer： Sangjoon Lee ,  Yonghwan Kwon ,  Jae Julien

公开(公告)号：US12287960B2

公开(公告)日：2025-04-29

申请号：US18131728

申请日：2023-04-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Sangjin Han ,  Yonghwan Kwon ,  Hyeonji Lee ,  Seokhyun Kim ,  Junggeun Kim ,  Hyunsoo Yuk

IPC: G06F3/04845 ,  G06F3/0354 ,  G06F3/0362 ,  G06F3/048

Abstract: An electronic device includes a display and a processor configured to control the display to display a user interface (UI) screen including a plurality of graphical user interface (GUI) items and a focus GUI, identify, based on a wheel input of a user, arrangement information about the plurality of GUI items, identify, based on the arrangement information, a possible movement direction of the focus GUI displayed at a location corresponding to one GUI item among the plurality of GUI items, based on the identified possible movement direction of the focus GUI including both a horizontal direction and a vertical direction, identify a movement direction of the focus GUI as the horizontal direction, and control the display to move the focus GUI based on a manipulation direction of the wheel input and the identified movement direction.

公开(公告)号：US12261103B2

公开(公告)日：2025-03-25

申请号：US17647144

申请日：2022-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon

IPC: H01L23/48 ,  H01L23/31 ,  H01L23/498 ,  H01L25/10 ,  H01L23/00

Abstract: A semiconductor package includes a semiconductor chip on a first redistribution substrate, a molding layer that covers the semiconductor chip, and a second redistribution substrate on the molding layer and that includes a dielectric layer, a redistribution pattern, and a conductive pad. The dielectric layer includes a lower opening that exposes the conductive pad, and an upper opening connected to the lower opening and that is wider than the lower opening. The semiconductor package also comprises a redistribution pad on the conductive pad and that covers a sidewall of the lower opening and a bottom surface of the upper opening. A top surface of the dielectric layer is located at a higher level than a top surface of the redistribution pad. The top surface of the redistribution pad is located on the bottom surface of the upper opening.

公开(公告)号：US20220375889A1

公开(公告)日：2022-11-24

申请号：US17646675

申请日：2021-12-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghwan Kwon ,  Yongjin Park

IPC: H01L23/00 ,  H01L23/498 ,  H01L23/31

Abstract: A semiconductor package includes a first redistribution structure, including a first insulating layer and a first redistribution layer disposed below the first insulating layer; a semiconductor chip disposed on the first redistribution structure, including a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer; an encapsulant disposed on the first redistribution structure that seals a portion of the semiconductor chip; a second redistribution structure, including a second redistribution layer disposed on the encapsulant; and a through via, including a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer and a via portion penetrating through the encapsulant and electrically connecting the pattern portion and the second redistribution layer. The connection terminal and the pattern portion are located at a first level and are electrically connected to each other at a second level lower than the first level.

公开(公告)号：US20220102256A1

公开(公告)日：2022-03-31

申请号：US17225178

申请日：2021-04-08

Applicant: Samsung Electronics Co., Ltd.

Inventor： Yonghwan Kwon

IPC: H01L23/498 ,  H01L23/538 ,  H01L25/18 ,  H01L23/00

Abstract: A fan-out semiconductor package includes: a support wiring structure including a support wiring conductive structure, a plurality of support wiring insulating layers including a first support wiring insulating layer having a recess area and a second support wiring insulating layer on the first support wiring insulating layer and enveloping the support wiring conductive structure, a pad layer enveloped by the second support wiring insulating layer and connected to the support wiring conductive structure, and an under-bump metallurgy (UBM) layer enveloped by the first support wiring insulating layer and connected to the pad layer; and a semiconductor chip on the support wiring structure, wherein the UBM layer includes a body portion and a protrusion protruding from the body portion and arranged in the recess area.

公开(公告)号：US09972605B2

公开(公告)日：2018-05-15

申请号：US15479100

申请日：2017-04-04

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon

IPC: H01L29/40 ,  H01L25/065 ,  H01L23/31 ,  H01L23/00 ,  H01L25/00 ,  H01L21/56

CPC classification number: H01L25/0657 ,  H01L21/4853 ,  H01L21/486 ,  H01L21/563 ,  H01L21/565 ,  H01L21/566 ,  H01L21/568 ,  H01L23/3114 ,  H01L23/3128 ,  H01L23/3178 ,  H01L23/3185 ,  H01L23/5383 ,  H01L23/5384 ,  H01L23/5389 ,  H01L24/02 ,  H01L24/24 ,  H01L24/73 ,  H01L24/82 ,  H01L24/92 ,  H01L24/96 ,  H01L25/065 ,  H01L25/50 ,  H01L2224/02379 ,  H01L2224/04105 ,  H01L2224/0557 ,  H01L2224/12105 ,  H01L2224/16145 ,  H01L2224/16146 ,  H01L2224/24137 ,  H01L2224/24146 ,  H01L2224/32145 ,  H01L2224/32225 ,  H01L2224/73204 ,  H01L2224/73209 ,  H01L2224/73253 ,  H01L2224/73259 ,  H01L2224/73267 ,  H01L2224/81005 ,  H01L2224/92124 ,  H01L2224/92224 ,  H01L2224/92225 ,  H01L2224/92244 ,  H01L2225/06544 ,  H01L2924/00

Abstract: A method for fabricating a fan-out wafer level package includes disposing a first semiconductor chip on a dummy substrate, forming a mold substrate on the first semiconductor chip and the dummy substrate, removing the dummy substrate to expose the first semiconductor chip, disposing a second semiconductor chip on the exposed first semiconductor chip, forming an insulating layer on the second semiconductor chip, the first semiconductor chip, and the mold substrate, and forming a plurality of redistribution lines that electrically connects the first semiconductor chip and the second semiconductor chip through the insulating layer.

公开(公告)号：US20240290739A1

公开(公告)日：2024-08-29

申请号：US18655471

申请日：2024-05-06

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Yonghwan Kwon ,  Yongjin Park

IPC: H01L23/00 ,  H01L23/31 ,  H01L23/498

CPC classification number: H01L24/08 ,  H01L23/3107 ,  H01L23/49822 ,  H01L23/49827 ,  H01L23/49838 ,  H01L2224/08235

Abstract: A semiconductor package includes a first redistribution structure, including a first insulating layer and a first redistribution layer disposed below the first insulating layer; a semiconductor chip disposed on the first redistribution structure, including a connection terminal electrically connected to the first redistribution layer and buried in the first insulating layer; an encapsulant disposed on the first redistribution structure that seals a portion of the semiconductor chip; a second redistribution structure, including a second redistribution layer disposed on the encapsulant; and a through via, including a pattern portion buried in the first insulating layer and electrically connected to the first redistribution layer and a via portion penetrating through the encapsulant and electrically connecting the pattern portion and the second redistribution layer. The connection terminal and the pattern portion are located at a first level and are electrically connected to each other at a second level lower than the first level.