公开(公告)号：US20240178202A1

公开(公告)日：2024-05-30

申请号：US18356035

申请日：2023-07-20

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Byeongchan KIM ,  Un-Byoung KANG ,  Jumyong PARK ,  Dongjoon OH ,  Jun Young OH ,  Jeongil LEE ,  Chungsun LEE

IPC: H01L25/10 ,  H01L23/00 ,  H01L23/498

CPC classification number: H01L25/105 ,  H01L23/49822 ,  H01L24/08 ,  H01L24/09 ,  H01L24/80 ,  H10B80/00

Abstract: A semiconductor device includes: a semiconductor layer including a wire and an electrical element; and a plurality of metal pads on a surface of the semiconductor layer, wherein the plurality of metal pads includes a first metal pad and a second metal pad, wherein the second metal pad is smaller in surface area or diameter on the surface of the semiconductor layer than the first metal pad, and wherein the second metal pad is between a first region of the surface of the semiconductor layer where the first metal pad is and a second region of the surface of the semiconductor layer where a surface metal density is zero (0).

公开(公告)号：US20230073690A1

公开(公告)日：2023-03-09

申请号：US17711370

申请日：2022-04-01

Applicant: Samsung Electronics Co., Ltd.

Inventor： Hyunsu HWANG ,  Junyun KWEON ,  Jumyong PARK ,  Solji SONG ,  Dongjoon OH ,  Chungsun LEE

IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544

Abstract: A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

公开(公告)号：US20210335688A1

公开(公告)日：2021-10-28

申请号：US17035145

申请日：2020-09-28

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Solji SONG ,  Jinho AN ,  Jeonggi JIN ,  Jinho CHUN ,  Juil CHOI

IPC: H01L23/31 ,  H01L23/48 ,  H01L23/00 ,  H01L21/768

Abstract: A semiconductor device is disclosed. The semiconductor device includes a via passivation layer disposed on an inactive surface of a substrate, a through-electrode vertically penetrating the substrate and the via passivation layer, a concave portion formed in the top surface of the via passivation layer and disposed adjacent to the through-electrode, and a via protective layer coplanar with the via passivation layer and the through-electrode and to fill the concave portion. In a horizontal cross-sectional view, the via protective layer has a band shape surrounding the through-electrode.

公开(公告)号：US20240312894A1

公开(公告)日：2024-09-19

申请号：US18668974

申请日：2024-05-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

IPC: H01L23/498

CPC classification number: H01L23/49838 ,  H01L23/49822

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.

公开(公告)号：US20230112006A1

公开(公告)日：2023-04-13

申请号：US17826521

申请日：2022-05-27

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Dongjoon OH ,  Unbyoung KANG ,  Byeongchan KIM ,  Jumyong PARK ,  Solji SONG ,  Chungsun LEE ,  Hyunsu HWANG

IPC: H01L25/18 ,  H01L23/00 ,  H01L23/48

Abstract: A semiconductor package includes: a first semiconductor chip including a first semiconductor substrate including a first active surface and a first inactive surface opposite to each other and a plurality of first chip pads on the first active surface; a second semiconductor chip including a second semiconductor substrate including a second active surface and a second inactive surface opposite to each other and a plurality of second chip pads on the second active surface, the second active surface being stacked on the first semiconductor chip to face the first inactive surface; a bonding insulation material layer interposed between the first semiconductor chip and the second semiconductor chip; and a plurality of bonding pads surrounded by the bonding insulation material layer to electrically connect the first semiconductor chip to the second semiconductor chip.

公开(公告)号：US20230070532A1

公开(公告)日：2023-03-09

申请号：US17726363

申请日：2022-04-21

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jumyong PARK ,  Unbyoung KANG ,  Byeongchan KIM ,  Solji SONG ,  Chungsun LEE

IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

公开(公告)号：US20220068779A1

公开(公告)日：2022-03-03

申请号：US17308643

申请日：2021-05-05

Applicant: Samsung Electronics Co., Ltd.

Inventor： Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Jeonggi JIN ,  Hyunsu HWANG

IPC: H01L23/498 ,  H01L23/538 ,  H01L23/00 ,  H01L25/10

Abstract: Disclosed are interconnection patterns and semiconductor packages including the same. The interconnection pattern comprises a first dielectric layer, a first interconnection pattern in the first dielectric layer, a first barrier layer between the first interconnection pattern and the first dielectric layer, a first top surface of the first barrier layer located at a level lower than that of a second top surface of the first dielectric layer and lower than that of a third top surface of the first interconnection pattern, a second barrier layer on the first barrier layer, the second barrier layer interposed between the first interconnection pattern and the first dielectric layer, a second dielectric layer on the first dielectric layer, the first interconnection pattern, and the second barrier layer, and a second interconnection pattern formed in the second dielectric layer and electrically coupled to the first interconnection pattern.

公开(公告)号：US20220037248A1

公开(公告)日：2022-02-03

申请号：US17364558

申请日：2021-06-30

Applicant: Samsung Electronics Co., Ltd.

Inventor： Ju-Il CHOI ,  Jumyong PARK ,  Jin Ho AN ,  Dongjoon OH ,  Chungsun LEE ,  Jeonggi JIN ,  Jinho CHUN

IPC: H01L23/498

Abstract: A semiconductor package includes a redistribution substrate that includes a first redistribution pattern and a second redistribution pattern that are at different levels from each other, and a semiconductor chip on the redistribution substrate and including a plurality of chip pads electrically connected to the first and second redistribution patterns. The first redistribution pattern includes a first metal pattern on a first dielectric layer, and a first barrier pattern between the first dielectric layer and a bottom surface of the first metal pattern. The second redistribution pattern includes a second metal pattern in a second dielectric layer, and a second barrier pattern between the second dielectric layer and a bottom surface of the second metal pattern and between the second dielectric layer and a sidewall of the second metal pattern.