公开(公告)号：US20240420754A1

公开(公告)日：2024-12-19

申请号：US18817678

申请日：2024-08-28

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G06F3/06 ,  G11C7/22 ,  G11C11/409

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20230317138A1

公开(公告)日：2023-10-05

申请号：US18330527

申请日：2023-06-07

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： DAE-SIK MOON ,  GIL-HOON CHA ,  KI-SEOK OH ,  CHANG-KYO LEE ,  YEON-KYU CHOI ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA ,  SEOK-HUN HYUN

IPC: G11C11/4076 ,  G11C7/22 ,  G06F3/06 ,  G11C11/409

CPC classification number: G11C11/4076 ,  G11C7/222 ,  G06F3/0673 ,  G11C11/409 ,  G06F3/0659 ,  G06F3/0604 ,  G06F3/0653

Abstract: A memory device includes a clock receiver configured to receive, from a memory controller, a write clock that is used to receive write data during a data write operation, a duty monitor configured to generate first monitoring information by monitoring a duty of the write clock, and a duty adjuster configured to adjust the duty of the write clock in response to a duty control signal and output an adjusted write clock. The memory device provides the first monitoring information to the memory controller, and receives the duty control signal, generated using the first monitoring information, from the memory controller.

公开(公告)号：US20210233575A1

公开(公告)日：2021-07-29

申请号：US17141357

申请日：2021-01-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  H03H7/38 ,  G11C7/10

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.

公开(公告)号：US20180342274A1

公开(公告)日：2018-11-29

申请号：US15918526

申请日：2018-03-12

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： YOUNG-HOON SON ,  SI-HONG KIM ,  CHANG-KYO LEE ,  JUNG-HWAN CHOI ,  KYUNG-SOO HA

IPC: G11C7/24 ,  G11C7/10 ,  H03H7/38

Abstract: A method of controlling on-die termination (ODT) in a multi-rank system including a plurality of memory ranks is provided. The method includes: enabling ODT circuits of the plurality of memory ranks into an initial state when the multi-rank system is powered on; enabling the ODT circuits of a write target memory rank and non-target memory ranks among the plurality of memory ranks during a write operation; and disabling the ODT circuit of a read target memory rank among the plurality of memory ranks while enabling the ODT circuits of non-target memory ranks among the plurality of memory ranks during a read operation.