STORAGE DEVICE AND OPERATING METHOD OF STORAGE DEVICE

    公开(公告)号:US20190122714A1

    公开(公告)日:2019-04-25

    申请号:US15995533

    申请日:2018-06-01

    Abstract: A storage device including a nonvolatile memory device including memory blocks and a controller connected with the nonvolatile memory device through data input and output lines and a data strobe line may be provided. The nonvolatile memory device and the controller may be configured to perform training on the data input and output lines by adjusting a delay of a data strobe signal sent through the data strobe line and adjust delays of the data input and output lines based on the training result.

    Electronic device including contact structure using magnet

    公开(公告)号:US12085994B2

    公开(公告)日:2024-09-10

    申请号:US18089087

    申请日:2022-12-27

    CPC classification number: G06F1/1656 G06F1/1624 G06F1/1652

    Abstract: An electronic device according to various embodiments of the disclosure may include: a housing including a first housing and a second housing, a wireless communication circuit, and at least one contact structure comprising a conductor, wherein the first housing may include a ground and the second housing may include a conductive portion, wherein, in a first state, the second housing may be configured to move in a first direction to be changed to a second state and, in a second state, the second housing may be configured to move in a second direction to be change to the first state, and wherein, in the first state, the at least one contact structure may be configured to electrically connect the ground of the first housing to the conductive portion of the second housing, and the wireless communication circuit may be configured to receive a signal by feeding power to a point of the conductive portion of the second housing.

    Search circuits, hammer address management circuits, and memory systems including the same

    公开(公告)号:US11107531B2

    公开(公告)日:2021-08-31

    申请号:US16806487

    申请日:2020-03-02

    Inventor: Hyungjin Kim

    Abstract: A search circuit includes a content-addressable memory (CAM) including a plurality of CAM cells configured to store a plurality of entry data, each entry data including a first bit corresponding to a least significant bit through a K-th bit corresponding to a most significant bit, the CAM configured to provide a plurality of matching signals indicating whether each of the plurality of entry data matches searching data, and a CAM controller configured to perform a partial searching operation such that the CAM controller applies comparison bits corresponding to a portion of the first through K-th bits as the searching data to the CAM and searches for target entry data among the plurality of entry data based on the plurality of matching signals indicating that the corresponding bits of the target entry data match the comparison bits.

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