公开(公告)号：US20240105765A1

公开(公告)日：2024-03-28

申请号：US18461408

申请日：2023-09-05

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Park ,  Intak Jeon ,  Hanjin Lim ,  Hyungsuk Jung

IPC: H01G4/30 ,  H10B12/00

CPC classification number: H01L28/92 ,  H10B12/0335 ,  H10B12/315

Abstract: A capacitor structure includes a first lower conductive pattern, a first capacitor, a first upper conductive pattern, a second lower conductive pattern, a second capacitor and a second upper conductive pattern. The first capacitor includes first lower electrodes, first upper electrodes and first dielectric structures. Each of the first dielectric structures are disposed between one of the first lower electrodes and a corresponding one of the first upper electrodes. The first upper conductive pattern is formed on and is electrically connected to the first upper electrodes. The second lower conductive pattern is spaced apart from the first lower conductive pattern disposed on the substrate. The second capacitor includes second lower electrodes, second upper electrodes and second dielectric structures. The second upper conductive pattern is formed on and is electrically connected to the second upper electrodes. The first and second conductive patterns are electrically insulated from each other.

公开(公告)号：US20240030024A1

公开(公告)日：2024-01-25

申请号：US18137339

申请日：2023-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Hanjin Lim ,  Hyungsuk Jung

IPC: H01L21/02 ,  H01L21/3105

CPC classification number: H01L21/0228 ,  H01L21/02181 ,  H01L21/02189 ,  H01L21/02205 ,  H01L21/31055

Abstract: In a method of a method of depositing a layer, a substrate is loaded on a substrate stage within a chamber. A precursor gas and a reaction gas are alternately supplied into the chamber to form at least one atomic layer. A surface of the at least one atomic layer is planarized by applying pressure on the surface of the at least one atomic layer to diffuse atoms located on the surface having a relatively high curvature. The precursor gas and the reaction gas are alternately supplied into the chamber to form at least one atomic layer on the planarized atomic layer.

公开(公告)号：US11784213B2

公开(公告)日：2023-10-10

申请号：US17315947

申请日：2021-05-10

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Park ,  Hanjin Lim ,  Haeryong Kim ,  Younglim Park ,  Cheoljin Cho

IPC: H01L49/02

CPC classification number: H01L28/60

Abstract: An integrated circuit device including a first electrode layer including a first metal and having a first thermal expansion coefficient; a dielectric layer on the first electrode layer, the dielectric layer including a second metal oxide including a second metal that is different from the first metal, and having a second thermal expansion coefficient that is less than the first thermal expansion coefficient; and a first stress buffer layer between the first electrode layer and the dielectric layer, the first stress buffer layer including a first metal oxide including the first metal, and being formed due to thermal stress of the first electrode layer and thermal stress of the dielectric layer.

公开(公告)号：US20230290811A1

公开(公告)日：2023-09-14

申请号：US18052562

申请日：2022-11-03

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Park ,  Hanjin Lim ,  Hyungsuk Jung

IPC: H01L29/00

CPC classification number: H01L28/56 ,  H01L28/60

Abstract: A semiconductor device includes a capacitor structure. The capacitor structure includes a bottom electrode, a dielectric layer, and a top electrode that are stacked in a first direction. The dielectric layer includes a first dielectric layer, a second dielectric layer stacked on the first dielectric layer in the first direction, and a first impurity provided in the first dielectric layer. The first dielectric layer includes a ferroelectric material, and the second dielectric layer includes an anti-ferroelectric material.

公开(公告)号：US20230165013A1

公开(公告)日：2023-05-25

申请号：US17991940

申请日：2022-11-22

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Park ,  Hanjin Lim

IPC: H01L27/11507

CPC classification number: H01L27/11507

Abstract: A semiconductor device includes a transistor disposed on a substrate; and a capacitor structure electrically connected to the transistor, wherein the capacitor structure includes a first electrode; a dielectric layer structure disposed on the first electrode; and a second electrode disposed on the dielectric layer structure, the dielectric layer structure includes an interfacial layer disposed on the first electrode; a first dielectric layer disposed on the interfacial layer and including any one of a ferroelectric material, an antiferroelectric material, and a combination of a ferroelectric material and an antiferroelectric material; an insertion layer disposed on the first dielectric layer; and a second dielectric layer disposed on the insertion layer and including a paraelectric material.

公开(公告)号：US20230164979A1

公开(公告)日：2023-05-25

申请号：US17931880

申请日：2022-09-13

Applicant: Samsung Electronics Co., Ltd.

Inventor： Jungmin Park ,  Hanjin Lim

IPC: H01L27/108

CPC classification number: H01L27/10814 ,  H01L27/10823 ,  H01L27/10855 ,  H01L27/10885

Abstract: A semiconductor device includes a first contact plug on a substrate, a capacitor, an insulating division layer, and a second contact plug. The capacitor includes first and second electrodes and a dielectric layer. The first electrode contacts an upper surface of the first contact plug, and extends in a vertical direction substantially perpendicular to an upper surface of the substrate. The second electrode is spaced apart from the first electrode, and extends in the vertical direction and includes lower and upper surfaces substantially coplanar with lower and upper surfaces, respectively, of the first electrode. The dielectric layer is on sidewalls of the first and second electrodes. The insulating division layer is formed between portions of the dielectric layer on the sidewalls of the first and second electrodes. The second contact plug contacts the upper surface of the second electrode.

公开(公告)号：US20200350256A1

公开(公告)日：2020-11-05

申请号：US16933544

申请日：2020-07-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Changseok Lee ,  Hyeonjin Shin ,  Seongjun Park ,  Donghyun Im ,  Hyun Park ,  Keunwook Shin ,  Jongmyeong Lee ,  Hanjin Lim

IPC: H01L23/532

Abstract: Example embodiments relate to a wiring structure, a method of forming the same, and an electronic device employing the same. The wiring structure includes a first conductive material layer and a nanocrystalline graphene layer on the first conductive material layer in direct contact with the metal layer.

公开(公告)号：US20240321943A1

公开(公告)日：2024-09-26

申请号：US18601032

申请日：2024-03-11

Applicant: SAMSUNG ELECTRONICS CO., LTD.

Inventor： Jungmin Park ,  Hanjin Lim ,  Hyungsuk Jung

IPC: H10B12/00

CPC classification number: H01L28/75 ,  H01L28/65 ,  H10B12/31 ,  H10B12/482 ,  H10B12/488

Abstract: A semiconductor memory device includes an upper electrode, a lower electrode, an anti-ferroelectric layer disposed between the upper electrode and the lower electrode and including an anti-ferroelectric, an oxide layer disposed on a first surface of the anti-ferroelectric layer and including a high dielectric material, and a metal oxide layer disposed on a second surface of the anti-ferroelectric layer opposite to the first surface. A thickness of each of the oxide layer and the metal oxide layer is less than a thickness of the anti-ferroelectric layer.

公开(公告)号：US20240292596A1

公开(公告)日：2024-08-29

申请号：US18489189

申请日：2023-10-18

Applicant: Samsung Electronics Co., Ltd.

Inventor： Intak Jeon ,  Jungmin Park ,  Hanjin Lim ,  Hyungsuk Jung

IPC: H10B12/00

CPC classification number: H10B12/315 ,  H10B12/033

Abstract: A semiconductor device includes a lower structure, a capacitor on the lower structure, the capacitor including a first bottom electrode, which is extended in a direction perpendicular to a bottom surface of the lower structure, and a second bottom electrode, which is provided on the first bottom electrode, a bottom supporting pattern supporting the first bottom electrode, and a top supporting pattern provided on the bottom supporting pattern to support the first bottom electrode. The first bottom electrode includes a first material, and the second bottom electrode may include a second material. A work function of the second material is greater than a work function of the first material.

公开(公告)号：US11901291B2

公开(公告)日：2024-02-13

申请号：US17235369

申请日：2021-04-20

Applicant: Samsung Electronics Co., Ltd.

Inventor： Cheoljin Cho ,  Jungmin Park ,  Hanjin Lim ,  Jaehyoung Choi

IPC: H01L23/528 ,  H01L49/02

CPC classification number: H01L23/5283 ,  H01L28/60 ,  H01L28/75 ,  H01L28/90

Abstract: A semiconductor device includes a landing pad on a substrate, a lower electrode on the landing pad, the lower electrode including an outer protective layer, a conductive layer between opposing sidewalls of the outer protective layer, and an inner protective layer between opposing sidewalls of the conductive layer, a first supporter pattern on a side surface of the lower electrode, the first supporter pattern including a supporter hole, a dielectric layer on a surface of each of the lower electrode and the first supporter pattern, and an upper electrode on the dielectric layer. The outer protective layer includes titanium oxide, the conductive layer includes titanium nitride, and the inner protective layer includes titanium silicon nitride. In a horizontal cross-sectional view, the outer protective layer has an arc shape that extends between the dielectric layer and the conductive layer.