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    SEMICONDUCTOR PACKAGE
    13.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20230074933A1

    公开(公告)日：2023-03-09

    申请号：US17728727

    申请日：2022-04-25

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngkun JEE ,  Unbyoung KANG ,  Sanghoon LEE ,  Chungsun LEE

    IPC: H01L25/065 ,  H01L23/00

    Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

    INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME
    14.
    发明申请
    INTERCONNECTION STRUCTURE AND SEMICONDUCTOR PACKAGE INCLUDING THE SAME 有权

    公开(公告)号：US20220059442A1

    公开(公告)日：2022-02-24

    申请号：US17230511

    申请日：2021-04-14

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Dongjoon OH ,  Junyun KWEON ,  Jumyong PARK ,  Jin Ho AN ,  Chungsun LEE ,  Hyunsu HWANG

    IPC: H01L23/498 ,  H01L23/31 ,  H01L23/538

    Abstract: Disclosed are interconnection structures and semiconductor packages. The interconnection structure includes a first dielectric layer and a first hardmask pattern that are sequentially stacked, and a first interconnection pattern that penetrates the first hardmask pattern and the first dielectric layer. The first hardmask pattern includes a dielectric material having an etch selectivity with respect to the first dielectric layer. The first interconnection pattern includes a via part, a first pad part, and a line part that are integrally connected to each other. The first pad part vertically overlaps the via part. The line part extends from the first pad part. A level of a bottom surface of the first pad part is lower than a level of a bottom surface of the line part.

    SEMICONDUCTOR PACKAGE
    15.
    发明申请
    SEMICONDUCTOR PACKAGE 有权

    公开(公告)号：US20250167178A1

    公开(公告)日：2025-05-22

    申请号：US19029370

    申请日：2025-01-17

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Youngkun JEE ,  Unbyoung KANG ,  Sanghoon LEE ,  Chungsun LEE

    IPC: H01L25/065 ,  H01L23/00 ,  H01L23/48

    Abstract: A semiconductor package includes a first semiconductor chip including a first semiconductor substrate, and a plurality of first through electrodes penetrating at least a portion of the first semiconductor substrate. A plurality of second semiconductors include a second semiconductor substrate, the plurality of second semiconductor chips being stacked on the first semiconductor chip. A plurality of bonding pads are arranged between the first semiconductor chip and the plurality of second semiconductor chips. A chip bonding insulating layer is arranged between the first semiconductor chip and the plurality of second semiconductor chips. At least one supporting dummy substrate is stacked on the plurality of second semiconductor chips and having a support bonding insulating layer arranged on a lower surface thereof.

    SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
    16.
    发明申请
    SEMICONDUCTOR DEVICE, SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME 有权

    公开(公告)号：US20250105181A1

    公开(公告)日：2025-03-27

    申请号：US18975625

    申请日：2024-12-10

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Jumyong PARK ,  Unbyoung KANG ,  Byeongchan KIM ,  Solji SONG ,  Chungsun LEE

    IPC: H01L23/00 ,  H01L23/48 ,  H01L25/065

    Abstract: A semiconductor package includes a first semiconductor chip having a first substrate, a first insulating layer on the first substrate, and a plurality of first bonding pads on the first insulating layer, and having a flat upper surface by an upper surface of the first insulating layer and upper surfaces of the plurality of first bonding pads; and a second semiconductor chip on the upper surface of the first semiconductor chip and having a second substrate, a second insulating layer below the second substrate and in contact with the first insulating layer, and a plurality of second bonding pads on the second insulating layer and in contact with the first bonding pads, respectively, wherein the first insulating layer includes an insulating interfacial layer in contact with the second insulating layer, embedded in the first insulating layer, and spaced apart from the plurality of first bonding pads.

    SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME
    19.
    发明公开
    SEMICONDUCTOR CHIP, SEMICONDUCTOR PACKAGE INCLUDING THE SAME, AND METHOD OF FABRICATING THE SAME 审中-公开

    公开(公告)号：US20240071942A1

    公开(公告)日：2024-02-29

    申请号：US18120826

    申请日：2023-03-13

    Applicant: SAMSUNG ELECTRONICS CO., LTD.

    Inventor： Young kun JEE ,  Jihwan HWANG ,  Chungsun LEE

    IPC: H01L23/538 ,  H01L23/00

    CPC classification number: H01L23/5386 ,  H01L23/5384 ,  H01L24/06 ,  H01L2224/06051 ,  H01L2224/06102 ,  H01L2224/08146

    Abstract: A semiconductor chip including a semiconductor substrate having first and second surfaces, a transistor on the first surface, a first interlayer dielectric layer on the transistor, a second interlayer dielectric layer on the first interlayer dielectric layer, a wiring line in the second interlayer dielectric layer, a first conductive pad on the second interlayer dielectric layer, a first passivation layer on the second interlayer dielectric layer, a second conductive pad in the first passivation layer, a through via penetrating the semiconductor substrate and the first interlayer dielectric layer to come into connection with the wiring line, a second passivation layer on the second surface, and a third conductive pad in the second passivation layer and connected to the through via. The first passivation layer has a first thickness 0.4 to 0.6 times a second thickness between the first surface and a top surface of the second passivation layer.

    WAFER STRUCTURE AND SEMICONDUCTOR DEVICE
    20.
    发明申请
    WAFER STRUCTURE AND SEMICONDUCTOR DEVICE 有权

    公开(公告)号：US20230073690A1

    公开(公告)日：2023-03-09

    申请号：US17711370

    申请日：2022-04-01

    Applicant: Samsung Electronics Co., Ltd.

    Inventor： Hyunsu HWANG ,  Junyun KWEON ,  Jumyong PARK ,  Solji SONG ,  Dongjoon OH ,  Chungsun LEE

    IPC: H01L23/00 ,  H01L23/522 ,  H01L23/544

    Abstract: A wafer structure includes a semiconductor substrate that includes a chip region and a scribe lane region. A first dielectric layer is on a first surface of the semiconductor substrate, a second dielectric layer is on the first dielectric layer. A dielectric pattern is between the first dielectric layer and the second dielectric layer. A through via that penetrates the first surface and a second surface at the chip region of the semiconductor substrate, and a conductive pad is in the second dielectric layer and on the through via. The dielectric pattern includes an etch stop pattern on the chip region of the semiconductor substrate and in contact with a bottom surface of the conductive pad, and an alignment key pattern on the scribe lane region of the semiconductor substrate.

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