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    Low cost multi-state magnetic memory
    12.
    发明授权
    Low cost multi-state magnetic memory 有权
    低成本多状态磁存储器

    公开(公告)号：US08330240B2

    公开(公告)日：2012-12-11

    申请号：US13213026

    申请日：2011-08-18

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: H01L29/82 ,  G11C11/00

    CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607

    Abstract: A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.

    Abstract translation: 多状态电流切换磁存储元件具有磁隧道结（MTJ），用于存储多于一位的信息。 MTJ包括固定层，阻挡层和不均匀的自由层。 在一个实施例中，当每个单元具有2位时，当四个不同电平的电流之一被施加到存储元件时，所施加的电流使MTJ的非均匀自由层切换到四个不同的磁状态之一。 MTJ的宽开关电流分布是非均匀自由层的宽晶粒尺寸分布的结果。

    Method for manufacturing high density non-volatile magnetic memory
    13.
    发明授权
    Method for manufacturing high density non-volatile magnetic memory 有权
    高密度非挥发性磁记忆体的制造方法

    公开(公告)号：US08802451B2

    公开(公告)日：2014-08-12

    申请号：US13610587

    申请日：2012-09-11

    Applicant: Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

    Inventor： Roger Klas Malmhall ,  Kimihiro Satoh ,  Jing Zhang ,  Parviz Keshtbod ,  Rajiv Yadav Ranjan

    IPC: H01L21/00

    CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/161 ,  H01L27/228

    Abstract: Methods of fabricating MTJ arrays using two orthogonal line patterning steps are described. Embodiments are described that use a self-aligned double patterning method for one or both orthogonal line patterning steps to achieve dense arrays of MTJs with feature dimensions one half of the minimum photo lithography feature size (F). In one set of embodiments, the materials and thicknesses of the stack of layers that provide the masking function are selected so that after the initial set of mask pads have been patterned, a sequence of etching steps progressively transfers the mask pad shape through the multiple mask layer and down through all of the MTJ cell layers to the form the complete MTJ pillars. In another set of embodiments, the MTJ/BE stack is patterned into parallel lines before the top electrode layer is deposited.

    Abstract translation: 描述使用两个正交线图案化步骤制造MTJ阵列的方法。 描述了使用用于一个或两个正交线图案化步骤的自对准双图案化方法来实现特征尺寸为最小光刻特征尺寸（F）的一半的MTJ的致密阵列的实施例。 在一组实施例中，选择提供掩模功能的层叠层的材料和厚度，使得在初始掩模焊盘组被图案化之后，一系列蚀刻步骤逐渐地将掩模焊盘形状传递通过多个掩模 通过所有的MTJ单元层的层和下层形成完整的MTJ柱。 在另一组实施例中，在沉积顶部电极层之前，将MTJ / BE叠层图案化成平行线。

    Method for manufacturing non-volatile magnetic memory
    14.
    发明授权
    Method for manufacturing non-volatile magnetic memory 有权
    制造非易失性磁记忆体的方法

    公开(公告)号：US08535952B2

    公开(公告)日：2013-09-17

    申请号：US12040827

    申请日：2008-02-29

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: H01L21/00

    CPC classification number: H01L43/12 ,  B82Y10/00 ,  B82Y25/00 ,  G11C11/16 ,  H01L27/228

    Abstract: In accordance with a method of the present invention, a method of manufacturing a magnetic random access memory (MRAM) cell and a corresponding structure thereof are disclosed to include a multi-stage manufacturing process. The multi-stage manufacturing process includes performing a front end on-line (FEOL) stage to manufacture logic and non-magnetic portions of the memory cell by forming an intermediate interlayer dielectric (ILD) layer, forming intermediate metal pillars embedded in the intermediate ILD layer, depositing a conductive metal cap on top of the intermediate ILD layer and the metal pillars, performing magnetic fabrication stage to make a magnetic material portion of the memory cell being manufactured, and performing back end on-line (BEOL) stage to make metal and contacts of the memory cell being manufactured.

    Abstract translation: 根据本发明的方法，公开了一种制造磁随机存取存储器（MRAM）单元及其相应结构的方法，以包括多级制造工艺。 多级制造过程包括通过形成中间层间电介质（ILD）层来形成前端在线（FEOL）级来制造存储单元的逻辑和非磁性部分，形成嵌入在中间ILD中的中间金属柱 层，在中间ILD层和金属柱的顶部上沉积导电金属帽，进行磁性制造阶段以制造存储单元的磁性材料部分，并执行后端在线（BEOL）阶段以制造金属 和正在制造的存储单元的触点。

    Low cost multi-state magnetic memory
    17.
    发明授权
    Low cost multi-state magnetic memory 有权
    低成本多状态磁存储器

    公开(公告)号：US08456897B2

    公开(公告)日：2013-06-04

    申请号：US13216997

    申请日：2011-08-24

    Applicant: Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    Inventor： Rajiv Yadav Ranjan ,  Parviz Keshtbod ,  Roger Klas Malmhall

    IPC: G11C11/00

    CPC classification number: H01L43/08 ,  G11C11/161 ,  G11C11/1673 ,  G11C11/5607

    Abstract: A multi-state current-switching magnetic memory element has a magnetic tunneling junction (MTJ), for storing more than one bit of information. The MTJ includes a fixed layer, a barrier layer, and a non-uniform free layer. In one embodiment, having 2 bits per cell, when one of four different levels of current is applied to the memory element, the applied current causes the non-uniform free layer of the MTJ to switch to one of four different magnetic states. The broad switching current distribution of the MTJ is a result of the broad grain size distribution of the non-uniform free layer.

    Abstract translation: 多状态电流切换磁存储元件具有磁隧道结（MTJ），用于存储多于一位的信息。 MTJ包括固定层，阻挡层和不均匀的自由层。 在一个实施例中，当每个单元具有2位时，当四个不同电平的电流之一被施加到存储元件时，所施加的电流使MTJ的非均匀自由层切换到四个不同的磁状态之一。 MTJ的宽开关电流分布是非均匀自由层的宽晶粒尺寸分布的结果。

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