公开(公告)号：US20210133020A1

公开(公告)日：2021-05-06

申请号：US17149041

申请日：2021-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kimihiko NAKAZAWA ,  Takahiro IRITA

IPC: G06F11/10 ,  G06F12/16

Abstract: A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.

公开(公告)号：US20210026788A1

公开(公告)日：2021-01-28

申请号：US17066998

申请日：2020-10-09

Applicant: Renesas Electronics Corporation

Inventor： Sho YAMANAKA ,  Toshiyuki HIRAKI ,  Yoshihiko HOTTA ,  Takahiro IRITA

IPC: G06F13/16 ,  G06F13/362 ,  G06F13/40 ,  G11C11/406

Abstract: A semiconductor device includes a first master and a second master configured to issue requests for accessing to a memory, a first request issuing controller coupled to the first master, and configured to hold the request issued from the first master, a second request issuing controller coupled to the second master, and configured to hold the request issued from the second master, a bus arbiter coupled to the first request issuing controller and the second request issuing controller, a memory controller coupled to the bus arbiter, and including a buffer configured to store the requests issued from the first master and the second master, and a central bus controller configured to grant access rights to the first request issuing controller and the second request issuing controller based on space information of the buffer.

公开(公告)号：US20190163648A1

公开(公告)日：2019-05-30

申请号：US16130847

申请日：2018-09-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kimihiko NAKAZAWA ,  Takahiro IRITA

IPC: G06F12/16 ,  G06F11/10

Abstract: A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.

公开(公告)号：US20180286885A1

公开(公告)日：2018-10-04

申请号：US16000967

申请日：2018-06-06

Applicant: Renesas Electronics Corporation

Inventor： Yusuke KANNO ,  Hiroyuki MIZUNO ,  Yoshihiko YASU ,  Kenji HIROSE ,  Takahiro IRITA

IPC: H01L27/118 ,  H03K3/03 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H03K17/16 ,  H03K3/037 ,  H01L27/02 ,  G06F17/50 ,  H01L23/528 ,  H01L27/00 ,  H01L29/78

CPC classification number: H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H03K19/0008 ,  H03K19/00346 ,  H01L2924/00

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.

公开(公告)号：US20160365358A1

公开(公告)日：2016-12-15

申请号：US15246796

申请日：2016-08-25

Applicant: Renesas Electronics Corporation

Inventor： Yusuke KANNO ,  Hiroyuki MIZUNO ,  Yoshihiko YASU ,  Kenji HIROSE ,  Takahiro IRITA

IPC: H01L27/118 ,  H03K17/16 ,  G11C11/419 ,  H03K3/03

CPC classification number: H01L27/11898 ,  G06F17/5068 ,  G06F17/5072 ,  G11C11/419 ,  H01L23/48 ,  H01L23/50 ,  H01L23/528 ,  H01L27/00 ,  H01L27/02 ,  H01L27/0203 ,  H01L27/0207 ,  H01L27/11807 ,  H01L29/7835 ,  H01L2027/11881 ,  H01L2924/0002 ,  H03K3/0315 ,  H03K3/0375 ,  H03K17/16 ,  H01L2924/00

Abstract: A semiconductor integrated circuit device having a control signal system for avoiding failure to check an indefinite signal propagation prevention circuit, for facilitating a check included in an automated tool, and for facilitating a power shutdown control inside a chip. In the semiconductor integrated circuit device, power shutdown priorities are provided by independent power domains (Area A to Area I). A method for preventing a power domain having a lower priority from being turned OFF when a circuit having a high priority is turned ON is also provided.