公开(公告)号：US20170153838A1

公开(公告)日：2017-06-01

申请号：US15355322

申请日：2016-11-18

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Katsushige MATSUBARA ,  Seiji MOCHIZUKI ,  Ryoji HASHIMOTO ,  Toshiyuki KAYA ,  Kimihiko NAKAZAWA ,  Takahiro IRITA ,  Tetsuji TSUDA

IPC: G06F3/06 ,  G06F7/544

CPC classification number: G06F3/0638 ,  G06F3/0604 ,  G06F3/0656 ,  G06F3/0673 ,  G06F7/544 ,  G06F2207/544 ,  H04N19/423

Abstract: Disclosed is a semiconductor device capable of performing compression and decompression with increased appropriateness. The semiconductor device includes a computing module and a memory control module. The computing module includes a computing unit and a compression circuit. The computing unit performs arithmetic processing. The compression circuit compresses data indicative of the result of arithmetic processing. The memory control module includes an access circuit and a decompression circuit. The access circuit writes compressed data into a memory and reads written data from the memory. The decompression circuit decompresses data read from the memory and outputs the decompressed data to the computing module.

公开(公告)号：US20210133020A1

公开(公告)日：2021-05-06

申请号：US17149041

申请日：2021-01-14

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kimihiko NAKAZAWA ,  Takahiro IRITA

IPC: G06F11/10 ,  G06F12/16

Abstract: A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.

公开(公告)号：US20190163648A1

公开(公告)日：2019-05-30

申请号：US16130847

申请日：2018-09-13

Applicant: RENESAS ELECTRONICS CORPORATION

Inventor： Kimihiko NAKAZAWA ,  Takahiro IRITA

IPC: G06F12/16 ,  G06F11/10

Abstract: A semiconductor device includes a master circuit which outputs a first write request signal for requesting to write data, a bus which receives the data and the first write request signal, a bus control unit which is arranged on the bus, generates an error detection code for the data and generates a second write request signal which includes second address information corresponding to first address information included in the first write request signal and memory controllers which each write the data into a storage area of an address designated by the first write request signal and writes the error detection code into a storage area of an address designated by the second write request signal in the storage areas of memories.