公开(公告)号：US11250197B1

公开(公告)日：2022-02-15

申请号：US17079727

申请日：2020-10-26

Applicant: QUALCOMM Incorporated

Inventor： Vinod Kumar Lakshmipathi ,  Venugopal Sanaka ,  Babu Suriamoorthy ,  Madan Krishnappa ,  Pavan Kumar Patibanda

IPC: G06F30/30 ,  G06F30/392 ,  G06F30/347 ,  G06F30/394 ,  G06F115/06 ,  G06F115/10 ,  G06F115/02 ,  G06F119/06

Abstract: Various embodiments may include integrated circuits (ICs) and methods for designing an integrated circuit (IC), such as a system-on-chip (SOC). Embodiments include methods for planning and producing ICs without communication channels, also referred to as channel-less ICs. Embodiments may include overlay hard macros that support routing and communication design without dedicated communication channels being needed between functional hard macros, such as cores of a SOC. Various embodiments may include an IC in which one or more interconnect hard macros and wires connecting a first functional hard macro, a second functional hard macro and the one or more interconnect hard macros are located within a third functional hard macro. In some embodiments, no communication channel may be present between the first functional hard macro, the second functional hard macro, and the third functional hard macro.

公开(公告)号：US09846612B2

公开(公告)日：2017-12-19

申请号：US14823879

申请日：2015-08-11

Applicant: QUALCOMM INCORPORATED

Inventor： Madan Krishnappa ,  Chinh Tran ,  Li Zhang ,  Alan Young ,  William Bainbridge ,  Bohuslav Rychlik

IPC: G06F11/10 ,  H03M13/00 ,  H03M13/11 ,  G06F1/32 ,  G06F11/30 ,  G11B20/18

CPC classification number: G06F11/10 ,  G06F1/3206 ,  G06F1/3296 ,  G06F11/1008 ,  G06F11/1048 ,  G06F11/3058 ,  G06F11/3062 ,  G11B20/1816 ,  H03M13/11 ,  H03M13/611 ,  H03M13/6505 ,  Y02D10/172

Abstract: Various embodiments of methods and systems for bit flip identification for debugging and/or power management in a system on a chip (“SoC”) are disclosed. Exemplary embodiments seek to identify bit flip occurrences near in time to the occurrences by checking parity values of data blocks as the data blocks are written into a memory component. In this way, bit flips occurring in association with a write transaction may be differentiated from bit flips occurring in association with a read transaction. The distinction may be useful, when taken in conjunction with various parameter levels identified at the time of a bit flip recognition, to debug a memory component or, when in a runtime environment, adjust thermal and power policies that may be contributing to bit flip occurrences.

公开(公告)号：US09612636B2

公开(公告)日：2017-04-04

申请号：US14497258

申请日：2014-09-25

Applicant: QUALCOMM Incorporated

Inventor： Matthew Levi Severson ,  Shih-Hsin Jason Hu ,  Dipti Ranjan Pal ,  Madan Krishnappa ,  Jeffrey Gemar ,  Noman Ahmed ,  Mohammad Tamjidi ,  Mark Kempfert

IPC: G06F1/32 ,  G06F1/26 ,  G06F9/44

CPC classification number: G06F1/26 ,  G06F1/32 ,  G06F1/3287 ,  G06F9/4405 ,  Y02D10/171

Abstract: A method for operating an electronic apparatus is provided. The method includes receiving a token, activating a power switch for powering up a core in response to the receiving the token, and outputting the token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. In one aspect, an electronic apparatus includes a power switch configured to power up to a core is provided. A power-switch control circuit is configured to receive a token, activate the power switch for powering up the core in response to receiving the token, output the received token based on a state of powering up the core. The outputting of the received token is delayed until the state of powering up the core is reached. A plurality of the power-switch control circuits is configured as a ring.