公开(公告)号：US10038060B2

公开(公告)日：2018-07-31

申请号：US15158653

申请日：2016-05-19

Applicant: QUALCOMM Incorporated

Inventor： Yong Ju Lee ,  Yang Du

IPC: H01L29/16 ,  H01L21/02 ,  H01L29/66 ,  H01L29/51 ,  H01L29/786 ,  H01L29/08 ,  H01L29/10 ,  H01L23/535 ,  H01L21/04 ,  H01L21/027

CPC classification number: H01L29/1606 ,  H01L21/02112 ,  H01L21/02378 ,  H01L21/02527 ,  H01L21/0272 ,  H01L21/0273 ,  H01L21/044 ,  H01L23/535 ,  H01L29/0847 ,  H01L29/1033 ,  H01L29/513 ,  H01L29/518 ,  H01L29/66045 ,  H01L29/6653 ,  H01L29/66742 ,  H01L29/78684

Abstract: An n-type metal-oxide-semiconductor (NMOS) transistor comprises a graphene channel with a chemically adsorbed nitrogen dioxide (NO2) layer formed thereon. The NMOS transistor may comprise a substrate having a graphene layer formed thereon and a gate stack formed on a portion of the graphene layer disposed in a channel region that further includes a spacer region. The gate stack may comprise the chemically adsorbed NO2 layer formed on the graphene channel, a high-k dielectric formed over the adsorbed NO2 layer, a gate metal formed over the high-k dielectric, and spacer structures formed in the spacer region. The adsorbed NO2 layer formed under the gate and the spacer structures may therefore attract electrons from the graphene channel to turn the graphene-based NMOS transistor off at a gate voltage (Vg) equal to zero, making the graphene-based NMOS transistor suitable for digital logic applications.

公开(公告)号：US20170329385A1

公开(公告)日：2017-11-16

申请号：US15666643

申请日：2017-08-02

Applicant: QUALCOMM Incorporated

Inventor： Hee Jun Park ,  Richard Gerard Hofmann ,  Yong Ju Lee

IPC: G06F1/32 ,  G06F13/16

CPC classification number: G06F1/3225 ,  G06F1/3287 ,  G06F13/1668 ,  Y02D10/171

Abstract: A low-power state current/power consumption for each volatile memory device in a plurality of volatile memory devices is obtained. Data is copied from a first set of the volatile memory devices to a second set of the volatile memory devices, where the second set of volatile memory devices has a lower current/power consumption than the first set of volatile memory devices. Additionally, a current/power consumption may be obtained for each memory bank within each of the plurality of volatile memory devices. Data is then copied from a first set of memory banks to a second set of memory banks within the same memory device in the second set of memory devices, where the second set of memory banks has lower current/power consumption than the first set of memory banks. The first set of volatile memory devices and/or first set of memory banks are then placed into a power-down state.