公开(公告)号：US20160077991A1

公开(公告)日：2016-03-17

申请号：US14484624

申请日：2014-09-12

Applicant: QUALCOMM Incorporated

Inventor： Randall John Pascarella ,  Jaya Prakash Subramaniam Ganasan ,  Thuong Quang Truong ,  Gurushankar Rajamani ,  Joseph Gerald McDonald ,  Thomas Philip Speier

IPC: G06F13/40 ,  G06F13/42

CPC classification number: G06F13/4013 ,  G06F13/1621 ,  G06F13/4027 ,  G06F13/4059 ,  G06F13/4221

Abstract: Bridging strongly ordered write transactions to devices in weakly ordered domains, and related apparatuses, methods, and computer-readable media are disclosed. In one aspect, a host bridge device is configured to receive strongly ordered write transactions from one or more strongly ordered producer devices. The host bridge device issues the strongly ordered write transactions to one or more consumer devices within a weakly ordered domain. The host bridge device detects a first write transaction that is not accepted by a first consumer device of the one or more consumer devices. For each of one or more write transactions issued subsequent to the first write transaction and accepted by a respective consumer device, the host bridge device sends a cancellation message to the respective consumer device. The host bridge device replays the first write transaction and the one or more write transactions that were issued subsequent to the first write transaction.

Abstract translation: 公布了对弱排序域中的设备进行强有序的写入事务，并且公开了相关设备，方法和计算机可读介质。 在一个方面，主桥设备被配置为从一个或多个强排序的生成器设备接收强有序的写事务。 主桥设备向弱排序域中的一个或多个消费者设备发出强有序的写事务。 主桥设备检测不被一个或多个消费者设备的第一消费者设备接受的第一写事务。 对于在第一写入事务之后发出并由相应的消费者设备接受的一个或多个写入事务中的每一个，主桥设备向相应的消费者设备发送取消消息。 主桥设备重播第一个写入事务以及在第一次写入事务之后发出的一个或多个写入事务。

公开(公告)号：US20150234761A1

公开(公告)日：2015-08-20

申请号：US14706203

申请日：2015-05-07

Applicant: QUALCOMM Incorporated

Inventor： Cristian Duroiu ,  Jaya Prakash Subramaniam Ganasan ,  Vinod Chamarty ,  Mark Michael Schaffer ,  Joshua Hirsch Stubbs ,  Robert Nicholson Gibson ,  Kris Tiri ,  Moinul Khan ,  Bohuslav Rychlik ,  Serag GadelRab ,  Simon Booth

IPC: G06F13/37 ,  G06F13/16 ,  G06F13/18 ,  G06F13/42

CPC classification number: G06F13/37 ,  G06F13/1626 ,  G06F13/18 ,  G06F13/362 ,  G06F13/4256 ,  G06F2213/0038 ,  G06F2213/0062 ,  G06F2213/0064 ,  G06F2213/36 ,  Y02D10/14

Abstract: Devices, systems, methods, and computer-readable mediums for arbitrating bus transactions on a communications bus based on health information are disclosed. Health information of master devices can be used to adjust priorities of bus transactions from master devices to meet quality of service requirements of the master devices. In one embodiment, a bus interconnect is provided and configured to communicate bus transactions from any of a plurality of master devices to slave device(s) coupled the bus interconnect. The bus interconnect is further configured to map health information for each of the plurality of master devices into virtual priority space. The bus interconnect is further configured to translate the virtual priority space into a physical priority level for each of the plurality of master devices. The bus interconnect is further configured to arbitrate bus transactions for the plurality of master devices based on physical priority level for the plurality of master devices.

Abstract translation: 公开了用于基于健康信息在通信总线上仲裁总线事务的设备，系统，方法和计算机可读介质。 主设备的健康信息可用于调整主设备总线事务的优先级，以满足主设备的服务质量要求。 在一个实施例中，总线互连被提供和配置为将总线事务从多个主设备中的任一个传送到耦合总线互连的从设备。 总线互连还被配置为将多个主设备中的每一个的健康信息映射到虚拟优先级空间中。 总线互连还被配置为将虚拟优先级空间转换为多个主设备中的每一个的物理优先级。 总线互连还被配置为基于多个主设备的物理优先级来仲裁多个主设备的总线事务。

公开(公告)号：US20140115221A1

公开(公告)日：2014-04-24

申请号：US13654653

申请日：2012-10-18

Applicant: QUALCOMM INCORPORATED

Inventor： Jaya Prakash Subramaniam Ganasan ,  Mark Michael Schaffer ,  Prudhvi N. Nooney ,  Perry Willmann Remaklus, JR.

IPC: G06F13/40

CPC classification number: G06F13/4027 ,  G06F1/3287 ,  G06F13/368 ,  G06F13/4004 ,  G06F15/17375 ,  Y02D10/14 ,  Y02D10/151

Abstract: Processor-based system hybrid ring bus interconnects, and related devices, systems, and methods are disclosed. In one embodiment, a processor-based system hybrid ring bus interconnect is provided. The processor-based system hybrid ring bus interconnect includes multiple ring buses, each having a bus width and configured to receive bus transaction messages from a requester device(s). The processor-based system hybrid ring bus interconnect also includes an inter-ring router(s) coupled to the ring buses. The inter-ring router(s) is configured to dynamically direct bus transaction messages among the ring buses based on bandwidth requirements of the requester device(s). Thus, less power is consumed than by a crossbar interconnect due to simpler switching configurations. Further, the inter-ring router(s) allows for provision of multiple ring buses that can be dynamically activated and deactivated based on bandwidth requirements. This provides conservation of power when full bandwidth requirements on the processor-based system hybrid ring bus interconnect are not required.

Abstract translation: 公开了基于处理器的系统混合环形总线互连以及相关设备，系统和方法。 在一个实施例中，提供了基于处理器的系统混合环形总线互连。 基于处理器的系统混合环形总线互连包括多个环形总线，每个环形总线具有总线宽度并且被配置为从请求者设备接收总线事务消息。 基于处理器的系统混合环形总线互连还包括耦合到环形总线的环形间路由器。 环形路由器被配置为基于请求者设备的带宽需求来动态地指导环形总线中的总线事务消息。 因此，由于更简单的开关配置，功率消耗比交叉开关互连更少。 此外，环形路由器允许提供可以基于带宽需求被动态地激活和去激活的多个环形总线。 当不需要基于处理器的系统混合环形总线互连的全带宽要求时，这提供了功率的保护。