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    PATCHED SHADING IN GRAPHICS PROCESSING
    11.
    发明申请
    PATCHED SHADING IN GRAPHICS PROCESSING 有权

    公开(公告)号：US20220068015A1

    公开(公告)日：2022-03-03

    申请号：US17522178

    申请日：2021-11-09

    Applicant: QUALCOMM Incorporated

    Inventor： Vineet GOEL ,  Andrew Evan Gruber ,  Donghyun Kim

    IPC: G06T15/80 ,  G06T15/00

    Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

    Patched shading in graphics processing
    12.
    发明授权
    Patched shading in graphics processing 有权
    修补阴影图形处理

    公开(公告)号：US09412197B2

    公开(公告)日：2016-08-09

    申请号：US13830145

    申请日：2013-03-14

    Applicant: QUALCOMM Incorporated

    Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

    IPC: G06T15/80 ,  G06T15/00

    CPC classification number: G06T15/80 ,  G06T15/00 ,  G06T15/005

    Abstract: Aspects of this disclosure generally relate to a process for rendering graphics that includes performing, with a hardware shading unit of a graphics processing unit (GPU) designated for vertex shading, vertex shading operations to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit is configured to receive a single vertex as an input and generate a single vertex as an output. The process also includes performing, with the hardware shading unit of the GPU, a geometry shading operation to generate one or more new vertices based on one or more of the vertex shaded vertices, wherein the geometry shading operation operates on at least one of the one or more vertex shaded vertices to output the one or more new vertices.

    Abstract translation: 本公开的方面通常涉及用于渲染图形的处理，其包括使用指定为顶点着色的图形处理单元（GPU）的硬件阴影单元执行遮蔽输入顶点的顶点着色操作，以便输出顶点着色顶点，其中 硬件单元被配置为接收单个顶点作为输入并且生成单个顶点作为输出。 该过程还包括利用GPU的硬件着色单元执行基于顶点着色顶点中的一个或多个以生成一个或多个新顶点的几何阴影操作，其中，几何阴影操作对一个 或多个顶点着色顶点，以输出一个或多个新顶点。

    Patched shading in graphics processing
    13.
    发明授权
    Patched shading in graphics processing 有权

    公开(公告)号：US11200733B2

    公开(公告)日：2021-12-14

    申请号：US16711098

    申请日：2019-12-11

    Applicant: QUALCOMM Incorporated

    Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

    IPC: G06T15/80 ,  G06T15/00 ,  G06T17/20 ,  G06T15/50

    Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

    MEMORY ADDRESS FLIPPING TO DETERMINE DATA CONTENT INTEGRITY IN GPU SUB-SYSTEM
    17.
    发明申请
    MEMORY ADDRESS FLIPPING TO DETERMINE DATA CONTENT INTEGRITY IN GPU SUB-SYSTEM 审中-公开

    公开(公告)号：US20190139263A1

    公开(公告)日：2019-05-09

    申请号：US15804707

    申请日：2017-11-06

    Applicant: QUALCOMM Incorporated

    Inventor： Andrew Evan Gruber ,  Rahul Gulati ,  Brendon Lewis Johnson ,  Jay Chunsup Yun ,  Alex Kwang Ho Jong ,  Donghyun Kim

    IPC: G06T7/00 ,  G06K9/00 ,  G08G1/16 ,  B60R1/00

    Abstract: Techniques of this disclosure may include processing data using one or more processors to produce a first image, including storing intermediate first results of processing the data in at least one internal memory of the one or more processors according to a first memory access pattern, processing the data using the one or more processors to produce a second image, including storing intermediate second results of processing the data in the at least one internal memory of the one or more processors according to a second memory access pattern, wherein the second memory access pattern is different than the first memory access pattern, comparing the first image to the second image, and generating an interrupt if the comparison indicates that the first image is different than the second image.

    Patched shading in graphics processing
    18.
    发明授权
    Patched shading in graphics processing 有权

    公开(公告)号：US12211143B2

    公开(公告)日：2025-01-28

    申请号：US18447155

    申请日：2023-08-09

    Applicant: QUALCOMM Incorporated

    Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

    IPC: G06T15/80 ,  G06T15/00 ,  G06T15/50 ,  G06T17/20

    Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

    Patched shading in graphics processing
    19.
    发明授权
    Patched shading in graphics processing 有权

    公开(公告)号：US11769294B2

    公开(公告)日：2023-09-26

    申请号：US17522178

    申请日：2021-11-09

    Applicant: QUALCOMM Incorporated

    Inventor： Vineet Goel ,  Andrew Evan Gruber ,  Donghyun Kim

    IPC: G06T15/80 ,  G06T17/20 ,  G06T15/00 ,  G06T15/50

    CPC classification number: G06T15/80 ,  G06T15/00 ,  G06T15/005 ,  G06T15/50 ,  G06T17/20

    Abstract: Aspects of this disclosure relate to a process for rendering graphics that includes performing, with a hardware unit of a graphics processing unit (GPU) designated for vertex shading, a vertex shading operation to shade input vertices so as to output vertex shaded vertices, wherein the hardware unit adheres to an interface that receives a single vertex as an input and generates a single vertex as an output. The process also includes performing, with the hardware unit of the GPU designated for vertex shading, a hull shading operation to generate one or more control points based on one or more of the vertex shaded vertices, wherein the one or more hull shading operations operate on at least one of the one or more vertex shaded vertices to output the one or more control points.

    COMPUTER PROCESSING UNIT INTRA-FRAME CLOCK AND VOLTAGE SCALING BASED ON GRAPHICS APPLICATION AWARENESS
    20.
    发明申请
    COMPUTER PROCESSING UNIT INTRA-FRAME CLOCK AND VOLTAGE SCALING BASED ON GRAPHICS APPLICATION AWARENESS 有权

    公开(公告)号：US20210271287A1

    公开(公告)日：2021-09-02

    申请号：US16804045

    申请日：2020-02-28

    Applicant: QUALCOMM Incorporated

    Inventor： Edwin Jose ,  Ravi Jenkal ,  Donghyun Kim

    IPC: G06F1/08 ,  G06F9/48 ,  G06F1/3206 ,  G06F9/38

    Abstract: Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

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