公开(公告)号：US20180294164A1

公开(公告)日：2018-10-11

申请号：US16009352

申请日：2018-06-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  ATSUSHI HARIKAI

IPC: H01L21/3065 ,  H01L21/78 ,  H01L21/687 ,  H01L21/683 ,  H01L21/67 ,  H01L21/308 ,  H01L21/677

CPC classification number: H01L21/3065 ,  H01L21/30655 ,  H01L21/308 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/677 ,  H01L21/6831 ,  H01L21/68742 ,  H01L21/68785 ,  H01L21/78

Abstract: The yield of a product is improved when a substrate held by a conveyance carrier is subjected to a plasma treatment. A method of manufacturing an electronic component includes preparing a substrate which is bonded to a holding sheet of a conveyance carrier, the conveyance carrier including the holding sheet and a frame disposed on an outer peripheral portion of the holding sheet, the substrate having a circuit layer; heating the holding sheet after preparing the substrate; cooling the holding sheet after heating the holding sheet; and plasma etching the substrate to singulate the substrate into the electronic component in a state that the substrate is placed above a stage included in a plasma treatment apparatus and the substrate is in contact with the stage via the holding sheet.

公开(公告)号：US20170345781A1

公开(公告)日：2017-11-30

申请号：US15594696

申请日：2017-05-15

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  AKIHIRO ITOU ,  KATSUMI TAKANO ,  MITSURU HIROSHIMA

IPC: H01L23/00 ,  H01L23/498 ,  H01L21/687 ,  H01L21/67 ,  H01L21/48 ,  H05K13/04 ,  B44C1/22

CPC classification number: H01L24/11 ,  B44C1/227 ,  H01L21/4853 ,  H01L21/67069 ,  H01L21/68742 ,  H01L23/49811 ,  H01L24/13 ,  H01L2224/11 ,  H05K13/0465

Abstract: An element chip manufacturing method includes a preparation process of preparing a substrate which includes a first surface having an exposed bump and a second surface opposite to the first surface and includes a plurality of element regions defined by dividing regions, a bump embedding process of embedding at least a head top part of the bump into the adhesive layer, a mask forming process of forming a mask in the second surface. The method for manufacturing the element chip includes a holding process of arranging the first surface to oppose a holding tape supported on a frame and holding the substrate on the holding tape, a placement process of placing the substrate on a stage provided inside of a plasma processing apparatus through the holding tape, after the mask forming process and the holding process.

公开(公告)号：US20170263500A1

公开(公告)日：2017-09-14

申请号：US15426199

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  SHOGO OKITA ,  MITSURU HIROSHIMA ,  TUTOMU SAKURAI ,  NORIYUKI MATSUBARA

IPC: H01L21/78 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01J2237/334 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6831

Abstract: The method includes a laser scribing step of forming an opening including an exposing portion, where the first layer is exposed, by irradiating the dividing region of the substrate with laser light from the first main surface side, forming a remaining region on which the second layer in the dividing region remains around the opening other than the exposing portion, and forming a first damaged region of a surface layer portion of the first layer including the exposing portion and a second damaged region of a surface layer portion of the first layer to be covered by the remaining region on the first layer of the dividing region.

公开(公告)号：US20170092527A1

公开(公告)日：2017-03-30

申请号：US15258717

申请日：2016-09-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： ATSUSHI HARIKAI ,  SHOGO OKITA ,  NORIYUKI MATSUBARA

IPC: H01L21/683 ,  H01L21/78

CPC classification number: H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L2221/68327 ,  H01L2221/6834

Abstract: In a plasma processing process used for a method of manufacturing element chips by which a plurality of element chips are manufactured by dividing a substrate having a plurality of element regions, the substrate is exposed to first plasma, and thereby the substrate is divided into element chips, and the element chips having first surfaces, second surfaces, and side surfaces connecting the first surfaces to the second surfaces are held with an interval between the element chips on the carrier. The element chips are exposed to second plasma which uses a mixed gas of fluorocarbon and helium as a raw material gas, and thereby a protection film covering the side surfaces is formed, and a conductive material is prevented from creeping up to the side surfaces during a mounting process.

公开(公告)号：US20180342424A1

公开(公告)日：2018-11-29

申请号：US15952342

申请日：2018-04-13

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI ,  AKIHIRO ITOU

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/311 ,  H01L21/027 ,  G03F7/20 ,  G03F7/09 ,  G03F7/32 ,  G03F7/039 ,  G03F7/16

CPC classification number: H01L21/78 ,  G03F7/039 ,  G03F7/091 ,  G03F7/16 ,  G03F7/168 ,  G03F7/2002 ,  G03F7/2022 ,  G03F7/32 ,  H01J37/32724 ,  H01J2237/334 ,  H01L21/0274 ,  H01L21/3065 ,  H01L21/308 ,  H01L21/31138

Abstract: A semiconductor chip manufacturing method includes forming a mask on a surface of a semiconductor wafer, forming an opening on the mask, exposing a dividing region of the semiconductor wafer, a rear surface of the semiconductor wafer is held by a dicing tape via an adhesive layer, singulating the semiconductor wafer into a plurality of semiconductor chips by etching the semiconductor wafer exposed to the opening with a first plasma until the semiconductor wafer reaches a rear surface, removing the mask so that the plurality of element chips from which the mask is removed are held by the holding sheet via the adhesive layer.At the time of removing the mask, the mask is removed from an alkaline developer having a dissolution rate of the mask larger than a dissolution rate of the adhesive layer.

公开(公告)号：US20180158713A1

公开(公告)日：2018-06-07

申请号：US15822568

申请日：2017-11-27

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  ATSUSHI HARIKAI ,  NORIYUKI MATSUBARA ,  AKIHIRO ITOU

IPC: H01L21/683 ,  H01L21/311 ,  H01L21/78 ,  H01L21/304 ,  H01L23/00

CPC classification number: H01L21/6836 ,  H01J37/00 ,  H01L21/304 ,  H01L21/31138 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/78 ,  H01L24/13 ,  H01L24/95 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/6834 ,  H01L2224/95001

Abstract: Provided is a method of manufacturing a semiconductor chip, the method comprising: preparing a plurality of semiconductor chips, each of which has a surface to which a BG tape is stuck, and a rear surface to which a DAF is stuck, and which are held spaced from each other by the BG tape and the DAF, exposing the DAF between semiconductor chips that are adjacent to each other when viewed from the surface side, by stripping the BG tape from the surface of each of the plurality of semiconductor chips, etching the DAF that is exposed between the semiconductor chips that are adjacent to each other, by irradiating the plurality of semiconductor chips held on the DAF, with plasma.

公开(公告)号：US20170263524A1

公开(公告)日：2017-09-14

申请号：US15426181

申请日：2017-02-07

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  MITSURU HIROSHIMA ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI

IPC: H01L23/31 ,  H01L21/56 ,  H01L21/311 ,  H01L23/544 ,  H01L21/268 ,  H01L21/78

CPC classification number: H01L23/3192 ,  H01L21/0212 ,  H01L21/02274 ,  H01L21/0337 ,  H01L21/268 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/311 ,  H01L21/31116 ,  H01L21/31138 ,  H01L21/56 ,  H01L21/67109 ,  H01L21/6831 ,  H01L21/6836 ,  H01L21/78 ,  H01L23/3185 ,  H01L23/544 ,  H01L23/562 ,  H01L2221/68327 ,  H01L2221/68381

Abstract: A method for manufacturing an element chip includes a protection film stacking step of staking a protection film to the element region, and the dividing region, the part of the exposed second damaged region and a protection film etching step of removing a part of the protection film which is stacked on the dividing region and the protection film which is stacked on the element region by exposing the substrate to second plasma and remaining the protection film for covering the part of the second damaged region. Furthermore, the method for manufacturing an element chip includes a plasma dicing step of dividing the substrate to a plurality of element chips by exposing the substrate to third plasma in a state where the second main surface is supported by a supporting member.

公开(公告)号：US20170263502A1

公开(公告)日：2017-09-14

申请号：US15428477

申请日：2017-02-09

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  ATSUSHI HARIKAI ,  AKIHIRO ITOU ,  NORIYUKI MATSUBARA ,  BUNZI MIZUNO

IPC: H01L21/78 ,  H01L21/3065 ,  H01L21/683 ,  H01L21/311 ,  H01L21/67

CPC classification number: H01L21/78 ,  H01L21/3065 ,  H01L21/30655 ,  H01L21/31116 ,  H01L21/67069 ,  H01L21/67109 ,  H01L21/6831 ,  H01L21/6833 ,  H01L21/6836 ,  H01L21/68742 ,  H01L2221/68327 ,  H01L2221/68336 ,  H01L2221/68381

Abstract: The method for manufacturing an element chip includes a mounting step and a plasma dicing step. In the mounting step, a semiconductor substrate with flexibility, which has a first main surface and a second main surface located at an opposite side of the first main surface, which has a plurality element regions and a dividing region for defining the element regions, and on which a mask for covering the first main surface in the element region and for exposing the first main surface in the dividing region is formed, is mounted on a stage. In the plasma dicing step, the semiconductor substrate is diced into a plurality of element chips including the element; region by exposing the first main surface side of the semiconductor substrate to plasma on the stage and etching from the first main surface side to the second main surface while forming a groove on the dividing region.

公开(公告)号：US20170263501A1

公开(公告)日：2017-09-14

申请号：US15427380

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： BUNZI MIZUNO ,  SHOGO OKITA ,  NORIYUKI MATSUBARA ,  ATSUSHI HARIKAI ,  MITSURU HIROSHIMA

IPC: H01L21/78 ,  H01L29/30 ,  H01L23/31 ,  H01L21/56 ,  H01L21/311

CPC classification number: H01L21/78 ,  H01L21/311 ,  H01L21/56 ,  H01L21/561 ,  H01L23/3171 ,  H01L23/3185 ,  H01L29/30

Abstract: A method for manufacturing an element chip includes a laser dicing step of dividing the substrate to a plurality of element chips including the element region by irradiating the dividing region of the substrate with laser light, in a state of supported by a supporting member and forming a damaged region on an end surface of the element chip. Furthermore, the method for manufacturing an element chip includes a protection film stacking step of stacking a protection film on the first main surface and the end surface of the element chip, after the laser dicing step and a protection film etching step of removing the protection film stacked on the first main surface through etching the protection film anisotropically by exposing the element chip to plasma, after the protection film stacking, step and remaining the protection film for covering the damaged region.

公开(公告)号：US20170263462A1

公开(公告)日：2017-09-14

申请号：US15427561

申请日：2017-02-08

Applicant: Panasonic Intellectual Property Management Co., Ltd.

Inventor： SHOGO OKITA ,  ATSUSHI HARIKAI

IPC: H01L21/3065 ,  H01L23/544 ,  H01L21/78

CPC classification number: H01L21/3065 ,  H01L21/30655 ,  H01L21/31138 ,  H01L21/67109 ,  H01L21/67115 ,  H01L21/6831 ,  H01L21/68742 ,  H01L21/68785 ,  H01L21/78 ,  H01L23/544 ,  H01L2223/5446

Abstract: A manufacturing method of an element chip includes a preparation process of adhering a holding sheet to the first main surface of a substrate so as to prepare the substrate held by the holding sheet, a plasma dicing process of performing plasma etching on the isolation region of the substrate to the first main surface so as to divide the substrate into the plurality of element chips. The plasma dicing process includes a first plasma etching process of performing plasma etching on a the isolation region partially in a thickness direction while a cooling gas is supplied between the stage and the holding sheet, and a second plasma etching process of stopping a supply of the cooling gas after the first plasma etching process, and performing plasma etching on a remaining portion of the isolation region.