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    PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD
    12.
    发明申请
    PLASMA PROCESSING APPARATUS AND PLASMA PROCESSING METHOD 有权
    等离子体加工设备和等离子体处理方法

    公开(公告)号：US20160293456A1

    公开(公告)日：2016-10-06

    申请号：US15000789

    申请日：2016-01-19

    Applicant: Panasonic Intellectual Property Management Co., Ltd.

    Inventor： Shogo Okita ,  Atsushi Harikai ,  Noriyuki Matsubara

    IPC: H01L21/677 ,  H01L21/3065 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78

    CPC classification number: H01L21/3065 ,  H01J37/32568 ,  H01J37/32697 ,  H01J37/32715 ,  H01J37/32724 ,  H01L21/67109 ,  H01L21/6833 ,  H01L21/6836 ,  H01L21/68742 ,  H01L21/78 ,  H01L2221/68327

    Abstract: A plasma processing apparatus includes: a reaction chamber; a plasma generation unit; a stage disposed inside the reaction chamber; an electrostatic chuck mechanism including an electrode portion inside the stage; a heater inside the stage; a support portion which supports a conveyance carrier between a stage-mounted position on the stage and a transfer position distant from the stage upward; and an elevation mechanism which elevates and lowers the support portion relative to the stage. In a case in which the conveyance carrier is mounted on the stage by lowering the support portion, application of voltage to the electrode portion is started in a state that the stage is being heated, and the plasma generation unit generates plasma after at least a part of an outer circumferential portion of a holding sheet holding the conveyance carrier contacts the stage and also after the heating of the stage is stopped.

    Abstract translation: 一种等离子体处理装置，包括：反应室; 等离子体发生单元; 设置在反应室内的阶段; 静电吸盘机构，其包括在所述平台内部的电极部分; 舞台内的加热器; 支撑部分，其支撑在舞台上的舞台安装位置和远离舞台的传送位置之间的传送载体; 以及升降机构，其使支撑部相对于台升高并降低。 在通过降低支撑部分将输送载体安装在载台上的情况下，在加热阶段的状态下开始对电极部施加电压，等离子体产生单元在至少一部分之后产生等离子体 保持输送载体的保持片的外周部与台架接触，并且在台架的加热停止之后。

    Manufacturing process of element chip using laser grooving and plasma-etching
    14.
    发明授权
    Manufacturing process of element chip using laser grooving and plasma-etching 有权

    公开(公告)号：US11145548B2

    公开(公告)日：2021-10-12

    申请号：US16362933

    申请日：2019-03-25

    Applicant: Panasonic Intellectual Property Management Co., Ltd.

    Inventor： Hidefumi Saeki ,  Atsushi Harikai ,  Shogo Okita

    IPC: H01L21/78 ,  H01L23/544 ,  H01L21/268 ,  B23K26/00 ,  B23K26/364 ,  H01L21/3065

    Abstract: A manufacturing process of an element chip comprises a preparing step for preparing a substrate having first and second sides opposed to each other, the substrate containing a semiconductor layer, a wiring layer and a resin layer formed on the first side, and the substrate including a plurality of dicing regions and element regions defined by the dicing regions. Also, the manufacturing process comprises a laser grooving step for irradiating a laser beam onto the dicing regions to form grooves so as to expose the semiconductor layer along the dicing regions. Further, the manufacturing process comprises a dicing step for plasma-etching the semiconductor layer along the dicing regions through the second side to divide the substrate into a plurality of the element chips. The laser grooving step includes a melting step for melting a surface of the semiconductor layer exposed along the dicing regions.

    Element chip manufacturing method
    15.
    发明授权
    Element chip manufacturing method 有权

    公开(公告)号：US10964597B2

    公开(公告)日：2021-03-30

    申请号：US16567047

    申请日：2019-09-11

    Applicant: Panasonic Intellectual Property Management Co., Ltd.

    Inventor： Atsushi Harikai ,  Shogo Okita ,  Noriyuki Matsubara ,  Hidefumi Saeki ,  Akihiro Itou

    IPC: H01L21/78 ,  H01L21/68 ,  H01L21/683

    Abstract: An element chip manufacturing method including: a preparing step of preparing a first conveying carrier including a holding sheet and a frame, and a substrate held on the holding sheet, the holding sheet having a first surface and a second surface opposite the first surface, the frame attached to at least part of a peripheral edge of the holding sheet; a placing step of placing the first conveying carrier holding the substrate, on a second conveying carrier; a preprocessing step of preprocessing the substrate, after the placing step; a removing step of removing the second conveying carrier, after the preprocessing step; and a dicing step of subjecting the substrate held on the first conveying carrier to plasma exposure, after the removing step, to form a plurality of element chips from the substrate.

    Element chip and manufacturing process thereof
    16.
    发明授权
    Element chip and manufacturing process thereof 有权

    公开(公告)号：US10923357B2

    公开(公告)日：2021-02-16

    申请号：US15899422

    申请日：2018-02-20

    Applicant: Panasonic Intellectual Property Management Co., Ltd.

    Inventor： Akihiro Itou ,  Atsushi Harikai ,  Noriyuki Matsubara ,  Shogo Okita

    IPC: H01L21/3065 ,  H01J37/32 ,  H01L21/687 ,  H01L21/683 ,  H01L21/78 ,  H01L21/311 ,  H01L21/67

    Abstract: Provided is a manufacturing process of an element chip, which comprises a preparation step, a setting step for setting the substrate on a stage, and a plasma-dicing step for dividing the substrate into a plurality of element chips, wherein the plasma-dicing step is achieved by repeatedly implementing etching routines each including an etching step for etching the second layer along the street regions to form a plurality of grooves and a depositing step for depositing a protective film on inner walls of the grooves, wherein the plasma-dicing step includes a first etching step for forming the grooves each having a first scallop on the inner wall thereof at a first pitch, and a second etching step for forming the grooves each having a second scallop on the inner wall thereof at a second pitch, and wherein the second pitch is greater than the first pitch.

    Method of manufacturing element chip
    19.
    发明授权
    Method of manufacturing element chip 有权

    公开(公告)号：US10607846B2

    公开(公告)日：2020-03-31

    申请号：US16103025

    申请日：2018-08-14

    Applicant: Panasonic Intellectual Property Management Co., Ltd.

    Inventor： Hidehiko Karasaki ,  Noriyuki Matsubara ,  Atsushi Harikai ,  Hidefumi Saeki

    IPC: H01L21/00 ,  H01L21/3065 ,  B23K26/0622 ,  H01L21/02 ,  H01L21/475 ,  H01L21/67 ,  H01L21/683 ,  H01L21/78

    Abstract: Method of manufacturing an element chip which can suppress residual debris in plasma dicing. A back surface of a semiconductor wafer is held on a dicing tape. Then, a surface of the wafer is coated with a mask that includes a water-insoluble lower mask and a water-soluble upper mask. Subsequently, an opening is formed in the mask by irradiating the mask with laser light to expose a dividing region. Then, the semiconductor wafer is caused to come into contact with water to remove the upper mask covering each of the element regions while leaving the lower layer. After that, the wafer is exposed to plasma to perform etching on the dividing region exposed from the opening until the etching reaches the back surface, thereby dicing the semiconductor wafer into a plurality of element chips. Thereafter, the lower layer mask left on the front surface of the semiconductor chips is removed.

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