公开(公告)号：US09678564B2

公开(公告)日：2017-06-13

申请号：US13725698

申请日：2012-12-21

Applicant: NXP B.V.

Inventor： Hamed Fatemi ,  Ajay Kapoor ,  Jose de Jesus Pineda de Gyvez ,  Juan Diego Echeverri Escobar

IPC: G06F13/20 ,  G06F1/32 ,  G06F13/24 ,  G06F13/364

CPC classification number: G06F1/329 ,  G06F13/24 ,  G06F13/364 ,  Y02D10/24

Abstract: An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.

公开(公告)号：US20170039103A1

公开(公告)日：2017-02-09

申请号：US14820417

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Nur Engin ,  Ajay Kapoor

IPC: G06F11/10 ,  G11C11/419 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G06F11/106 ,  G11C11/419 ,  G11C29/52

Abstract: An integrated circuit (IC) device including an SRAM module coupled to wrapper logic is disclosed. The wrapper logic includes an error correction code (ECC) encoder configured to encode input data in accordance with an ECC encoding scheme and output the encoded input data to the SRAM module, an ECC decoder configured to decode output data received from the SRAM module, output the decoded output data, and write decoding information back to the SRAM module, an error controller coupled to the ECC decoder that is configured to control the ECC decoder in accordance with the ECC encoding scheme, and a central controller coupled to the components of the wrapper logic and the SRAM module in order to control operations between the components of the wrapper logic and the SRAM module.

Abstract translation: 公开了一种包括耦合到封装逻辑的SRAM模块的集成电路（IC）装置。 包装器逻辑包括纠错码（ECC）编码器，其被配置为根据ECC编码方案对输入数据进行编码并将编码的输入数据输出到SRAM模块; ECC解码器，被配置为解码从SRAM模块接收的输出数据，输出 解码的输出数据和写解码信息返回到SRAM模块，耦合到ECC解码器的错误控制器，其被配置为根据ECC编码方案来控制ECC解码器;以及中央控制器，耦合到包装器的组件 逻辑和SRAM模块，以便控制包装逻辑和SRAM模块的组件之间的操作。

公开(公告)号：US20140181351A1

公开(公告)日：2014-06-26

申请号：US13725698

申请日：2012-12-21

Applicant: NXP B.V.

Inventor： Hamed Fatemi ,  Ajay Kapoor ,  Jose de Jesus Pineda de Gyvez ,  Juan Diego Echeverri Escobar

IPC: G06F13/40

CPC classification number: G06F1/329 ,  G06F13/24 ,  G06F13/364 ,  Y02D10/24

Abstract: An intelligent interrupt distributor balances interrupts (workload) in a highly parallelized system. The intelligent interrupt distributor distributes the interrupts between the processor cores. This allows lowering of voltage and frequency of individual processors and ensures that the overall system power consumption is reduced.

Abstract translation: 智能中断分配器平衡高并行化系统中的中断（工作负载）。 智能中断分配器在处理器内核之间分配中断。 这允许降低单个处理器的电压和频率，并确保降低整个系统功耗。

公开(公告)号：US11163346B2

公开(公告)日：2021-11-02

申请号：US16118749

申请日：2018-08-31

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Kristof Blutman ,  Juan Diego Echeverri Escobar ,  Jose de Jesus Pineda de Gyvez ,  Jurgen Geerlings ,  Hamed Fatemi

IPC: G06F1/26 ,  G06F1/32 ,  H02M3/07 ,  H02M3/137

Abstract: An electronic device including a power source providing a source voltage, a capacitor, a primary regulator circuit, an always-on load that is active during a low power mode, and a recycle control circuit. The primary regulator circuit receives the source voltage and has an output that maintains a charge on the capacitor during an active mode. The primary regulator circuit does not contribute to a charge on the capacitor during the low power mode. The recycle control circuit includes a select circuit and a select control circuit. The select circuit selects, based on a control signal, between the voltage of the capacitor and at least one supply voltage including or otherwise developed using the source voltage to provide power to the always-on load during the low power mode. The select control circuit provides the control signal to control power provided to the always-on load during the low power mode.

公开(公告)号：US10153639B2

公开(公告)日：2018-12-11

申请号：US14973575

申请日：2015-12-17

Applicant: NXP B.V.

Inventor： Ajay Kapoor

IPC: G05D3/12 ,  H02J3/12 ,  G06F1/32 ,  G05B15/02

Abstract: One example discloses an apparatus for power management, including: a current sink/source sensor configured to monitor a power-supply to inter-power-domain sink/source-current and to generate a current mismatch signal if the power-supply to inter-power-domain sink/source-current exceeds a threshold range; and a current imbalance controller coupled to receive the current mismatch signal and configured to generate a set of power-domain control signals; wherein the set of power-domain control signals reduce an absolute value of the power-supply to inter-power-domain sink/source-current.

公开(公告)号：US09917588B2

公开(公告)日：2018-03-13

申请号：US14794411

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Kristof Blutman ,  Ajay Kapoor ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03L5/00 ,  H03K19/0185 ,  H03K5/13

CPC classification number: H03K19/018514 ,  H03K3/356182 ,  H03K5/13 ,  H03K19/0185

Abstract: Aspects of the disclosure are directed to communications between respective power domains (circuitry) that may operate in a stacked arrangement in which the each domain operates over a different voltage range. A first circuit provides differential outputs that vary between first and second voltage levels, based on transitions of an input signal received from a first one of the power domains. First and second driver circuits are respectively coupled to the first and second differential outputs. A third driver circuit operates with the first and second circuits to level-shift the input signal from the first power domain to an output signal on a second power domain by driving an output circuit at the second voltage level in response to the input signal being at the first voltage level, and driving the output circuit at a third voltage level in response to the input signal being at the second voltage level.

公开(公告)号：US09912335B2

公开(公告)日：2018-03-06

申请号：US14794485

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Kristof Blutman ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03L5/00 ,  H03K19/0185 ,  G06F1/32 ,  H03K19/00 ,  H03K19/0175

CPC classification number: H03K19/018507 ,  G06F1/3234 ,  H03K19/0019 ,  H03K19/0175

Abstract: Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

公开(公告)号：US09614526B1

公开(公告)日：2017-04-04

申请号：US15019384

申请日：2016-02-09

Applicant: NXP B.V.

Inventor： Ajay Kapoor

IPC: H03K19/0175 ,  H03K3/356 ,  H03K3/012

CPC classification number: H03K19/017509 ,  G06F1/189 ,  G06F1/26 ,  G06F13/4004 ,  H03K3/012 ,  H03K3/356 ,  H04L12/40169

Abstract: Example apparatus for power-domain assignment, having: a first bus-to-switch interface; a second bus-to-switch interface; a first power-domain bus, coupled to the first bus-to-switch interface; a second power-domain bus, coupled to the second bus-to-switch interface. A set of I/O signal level shifters, coupled between the first and second power-domain buses; a switch including, a set of IP block power coupling outputs; a set of IP block I/O signal paths; and a selection signal input. The switch is coupled to the first and second bus-to-switch interfaces. Wherein, in response to receiving a first signal on the selection signal input, the switch is configure to couple the first power-domain bus to the set of IP block power coupling outputs; and wherein, in response to receiving a second signal on the selection signal input, the switch is configure to couple the second power-domain bus to the set of IP block power coupling outputs.

公开(公告)号：US20170039102A1

公开(公告)日：2017-02-09

申请号：US14820396

申请日：2015-08-06

Applicant: NXP B.V.

Inventor： Nur Engin ,  Ajay Kapoor

IPC: G06F11/10 ,  G11C29/42 ,  G11C29/52

CPC classification number: G06F11/1068 ,  G06F11/1048 ,  G11C11/419 ,  G11C29/42 ,  G11C29/50 ,  G11C29/52 ,  G11C2029/0411

Abstract: In accordance with an embodiment of the invention, an IC device is disclosed. In the embodiment, the IC device includes an array of bit cells of static random-access memory (SRAM), a multi-level digitization module configured to generate a value in a range of values from a bit cell in the array of bit cells, the range of values including more than two discrete values, an output buffer configured to store the generated values, and an error correction code (ECC) decoder configured to output error corrected values based on the stored values.

Abstract translation: 根据本发明的实施例，公开了一种IC器件。 在本实施例中，IC器件包括静态随机存取存储器（SRAM）的位单元阵列，多级数字化模块，被配置为从比特单元阵列中的比特单元生成值范围内的值， 包括多于两个离散值的值的范围，被配置为存储所生成的值的输出缓冲器，以及被配置为基于所存储的值输出误差校正值的纠错码（ECC）解码器。

公开(公告)号：US20170012627A1

公开(公告)日：2017-01-12

申请号：US14794485

申请日：2015-07-08

Applicant: NXP B.V.

Inventor： Ajay Kapoor ,  Kristof Blutman ,  Jose Pineda de Gyvez ,  Arnoud van der Wel

IPC: H03K19/0185

CPC classification number: H03K19/018507 ,  G06F1/3234 ,  H03K19/0019 ,  H03K19/0175

Abstract: Aspects of this disclosure are directed to level-shifting approaches with communications between respective circuits. As may be implemented in accordance with one or more embodiments characterized herein, a voltage level of communications passed between respective circuits are selectively shifted. Where the respective circuits operate under respective power domains that are shifted in voltage range relative to one another, the voltage level of the communications is shifted. This approach may, for example, facilitate power-savings for stacked circuits in which a low-level voltage of one circuit is provided as a high-level voltage for another circuit. When the respective circuits operate under a common power domain, the communications are passed directly between the respective circuits (e.g., bypassing any level-shifting, and facilitating fast communication).

Abstract translation: 本公开的方面涉及通过各个电路之间的通信的电平转换方法。 如可以根据本文特征的一个或多个实施例来实现的，在各个电路之间通过的通信的电压电平被选择性地移位。 在各个电路在相对于彼此在电压范围内移位的相应功率域下工作时，通信的电压电平发生偏移。 例如，该方法可以有助于对于其中提供一个电路的低电平电压作为另一个电路的高电平电压的堆叠电路的功率节省。 当各个电路在公共功率域下工作时，通信直接在相应的电路之间传递（例如，绕过任何电平转换，并促进快速通信）。