Abstract:
A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.
Abstract:
A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.
Abstract:
A circuit module includes a power amplifier, a switch, and a bypass capacitor. The power amplifier has a signal input node coupled to an input signal, a signal output node to generate an output signal, and a power input node coupled to a supply output signal of a supply modulator. The switch is coupled between the power input node of the power amplifier and the bypass capacitor. The bypass capacitor is an equivalently removable bypass capacitor coupled between the switch and a ground level.
Abstract:
Provided is a power supply circuit for a wireless mobile device having a plurality of power amplification components. The power supply circuit includes: a first DC-DC converter, for providing at least one constant output voltage (which is provided to the power amplification components) and/or at least one DC intermediate voltage; a second DC-DC converter, for providing a DC component of at least one time-varying output voltage; and at least one linear amplifier. When the at least one linear amplifier receives the at least one DC intermediate voltage from the first DC-DC converter, the at least one linear amplifier provides at least one AC component of the at least one time-varying output voltage. The DC component and the at least one AC component of the at least one time-varying output voltage are combined into the at least one time-varying output voltage and provided to the power amplification components.
Abstract:
A communication unit comprises a decimator configured to sample a variable control signal and output a reduced bandwidth variable control signal; and a multi-level power supply, MLPS, comprising an input and an output, wherein the input is coupled to the decimator and configured to receive the reduced bandwidth variable control signal and, in response thereto, the output delivers multi-level output voltages to supply a power amplifier, PA, module.
Abstract:
A calibration method is applied to a wireless communication device having a programmable tuner and a signal processing path. The calibration method includes at least the following steps: configuring the programmable tuner to have a plurality of different tuner states, wherein the signal processing path has a first end and a second end, and the programmable tuner is coupled to the second end; when the programmable tuner is configured to have one of the different tuner states, obtaining a measured reflection coefficient at the first end of the signal processing path; and calibrating mapping relationship between a reflection coefficient at the first end of the signal processing path and a reflection coefficient at the second end of the signal processing path according to the different tuner states and measured reflection coefficients associated with the different tuner states.