公开(公告)号：US12237949B2

公开(公告)日：2025-02-25

申请号：US18369798

申请日：2023-09-18

Applicant: MEDIATEK INC.

Inventor： Chung-Hsien Tsai ,  Che-Yu Chiang ,  Yu-Ting Liu ,  Tsung-Lin Lee ,  Chia-Sheng Peng ,  Ting-Ming Yang

IPC: H04L25/03 ,  H04L25/49

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.

公开(公告)号：US20240129167A1

公开(公告)日：2024-04-18

申请号：US18369798

申请日：2023-09-18

Applicant: MEDIATEK INC.

Inventor： Chung-Hsien Tsai ,  Che-Yu Chiang ,  Yu-Ting Liu ,  Tsung-Lin Lee ,  Chia-Sheng Peng ,  Ting-Ming Yang

IPC: H04L25/03

CPC classification number: H04L25/03057 ,  H04L25/49

Abstract: A communication receiver includes a first signal processing circuit and a second signal processing circuit. The first signal processing circuit includes a first feedforward equalizer and a decision circuit. The first feedforward equalizer processes a received signal to generate a first equalized signal. The decision circuit performs hard decision upon the first equalized signal to generate a first symbol decision signal. The second signal processing circuit includes a second feedforward equalizer, a decision feedforward equalizer, and a first decision feedback equalizer. The second feedforward equalizer processes the first equalized signal to generate a second equalized signal. The decision feedforward equalizer processes the first symbol decision signal to generate a third equalized signal. The first decision feedback equalizer generates a second symbol decision signal according to the second equalized signal and the third equalized signal.