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    DIGITAL TRANSMITTER AND METHOD FOR COMPENSATING MISMATCH IN DIGITAL TRANSMITTER
    11.
    发明申请
    DIGITAL TRANSMITTER AND METHOD FOR COMPENSATING MISMATCH IN DIGITAL TRANSMITTER 有权
    数字发射机和数字发射机误差补偿方法

    公开(公告)号：US20140348265A1

    公开(公告)日：2014-11-27

    申请号：US14281916

    申请日：2014-05-20

    Applicant: MEDIATEK INC.

    Inventor： Chi-Hsueh Wang ,  Yang-Chuan Chen ,  Hsiang-Hui Chang ,  Li-Shin Lai ,  Khurram Muhammad

    IPC: H04B1/04 ,  H04L25/08

    CPC classification number: H04B1/0475 ,  H03F1/02 ,  H03F3/2178 ,  H03F3/24 ,  H03G3/002 ,  H04B2001/045 ,  H04L25/08

    Abstract: A digital transmitter includes: a plurality of converting devices arranged to generate a plurality of converting signals according to a plurality of digital input signals; a compensation device arranged to generate at least one compensation signal according to the plurality of digital input signals; and a combining circuit arranged to output an amplified output signal according to the plurality of converting signals and the at least one compensation signal.

    Abstract translation: 数字发射机包括：多个转换装置，被配置为根据多个数字输入信号产生多个转换信号; 补偿装置，被配置为根据所述多个数字输入信号生成至少一个补偿信号; 以及组合电路，被配置为根据所述多个转换信号和所述至少一个补偿信号输出放大的输出信号。

    CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF
    16.
    发明申请
    CLOCK GENERATOR FOR GENERATING OUTPUT CLOCK HAVING NON-HARMONIC RELATIONSHIP WITH INPUT CLOCK AND RELATED CLOCK GENERATING METHOD THEREOF 有权
    用于产生具有输入时钟的非谐波关系的输出时钟的时钟发生器及其相关时钟生成方法

    公开(公告)号：US20130285724A1

    公开(公告)日：2013-10-31

    申请号：US13925858

    申请日：2013-06-25

    Applicant: MEDIATEK INC.

    Inventor： Robert Bogdan Staszewski ,  Chi-Hsueh Wang

    IPC: H03K5/13

    CPC classification number: H03K5/131 ,  H03L7/0996

    Abstract: A clock generator has an oscillator block and an output block. The oscillator block provides a second clock of multiple phases, and includes an oscillator and a delay locked loop (DLL). The oscillator is used to provide a first clock. The DLL is used to generate the second clock according to the first clock. The output block is used to receive the second clock and generate a third clock by selecting signals from the multiple phases, wherein the third clock has non-harmonic relationship the first clock.

    Abstract translation: 时钟发生器具有振荡器模块和输出模块。 振荡器模块提供多个相位的第二个时钟，并且包括一个振荡器和一个延迟锁定环（DLL）。 振荡器用于提供第一个时钟。 该DLL用于根据第一个时钟产生第二个时钟。 输出块用于接收第二时钟并通过选择来自多个相位的信号产生第三时钟，其中第三时钟具有第一时钟的非谐波关系。

    Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof
    17.
    发明授权
    Clock generator for generating output clock having non-harmonic relationship with input clock and related clock generating method thereof 有权
    时钟发生器，用于产生与输入时钟非谐波关系的输出时钟及其相关的时钟产生方法

    公开(公告)号：US08564348B1

    公开(公告)日：2013-10-22

    申请号：US13925858

    申请日：2013-06-25

    Applicant: Mediatek Inc.

    Inventor： Robert Bogdan Staszewski ,  Chi-Hsueh Wang

    IPC: H03L7/06

    CPC classification number: H03K5/131 ,  H03L7/0996

    Abstract: A clock generator has an oscillator block and an output block. The oscillator block provides a second clock of multiple phases, and includes an oscillator and a delay locked loop (DLL). The oscillator is used to provide a first clock. The DLL is used to generate the second clock according to the first clock. The output block is used to receive the second clock and generate a third clock by selecting signals from the multiple phases, wherein the third clock has non-harmonic relationship the first clock.

    Abstract translation: 时钟发生器具有振荡器模块和输出模块。 振荡器模块提供多个相位的第二个时钟，并且包括一个振荡器和一个延迟锁定环（DLL）。 振荡器用于提供第一个时钟。 该DLL用于根据第一个时钟产生第二个时钟。 输出块用于接收第二时钟并通过选择来自多个相位的信号产生第三时钟，其中第三时钟在第一时钟具有非谐波关系。

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