公开(公告)号：US09867135B1

公开(公告)日：2018-01-09

申请号：US15425183

申请日：2017-02-06

Applicant: MEDIATEK INC.

Inventor： Shao-Wei Feng ,  Shih-Chi Shen ,  Tso-Mo Chen ,  Chun-Ming Kuo

IPC: H03L7/26 ,  H04W52/02 ,  H03L7/16 ,  H03B5/32

CPC classification number: H04W52/029 ,  G06F7/68 ,  H03K5/00006 ,  H03L7/16 ,  H04W52/0287 ,  Y02D70/00

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a reference clock signal processor. The frequency synthesizer circuit receives a processed reference clock signal and generates a radio-frequency clock signal according to the processed reference clock signal. The reference clock signal processor receives an original reference clock signal from an oscillator and processes the original reference clock signal according to an indication signal to generate the processed reference clock signal. The indication signal is generated according to a required reference clock frequency of a communications apparatus. When the required reference clock frequency is high, a frequency of the processed reference clock signal is a multiple of a frequency of the original reference clock signal, and when the required reference clock frequency is low, the frequency of the original reference clock signal is a multiple of the frequency of the processed reference clock signal.

公开(公告)号：US09966986B1

公开(公告)日：2018-05-08

申请号：US15389708

申请日：2016-12-23

Applicant: MEDIATEK INC.

Inventor： Shih-Chi Shen ,  Shao-Wei Feng ,  Chun-Ming Kuo ,  Chi-Hsueh Wang ,  Ang-Sheng Lin

IPC: H04B1/18 ,  H04B1/40 ,  H04W52/02

CPC classification number: H04B1/40 ,  H03L7/0994 ,  H03L7/18 ,  H03L2207/50 ,  H04W52/02 ,  H04W52/0216 ,  H04W52/0235 ,  H04W52/0274 ,  H04W52/0287

Abstract: A frequency-generating circuit includes a frequency synthesizer circuit and a controller. The frequency synthesizer circuit generates a radio-frequency clock signal according to a reference clock signal and a channel number. The controller is coupled to the frequency synthesizer circuit, generates a power-down control signal for controlling at least a portion of the frequency synthesizer circuit to power down. The frequency synthesizer circuit includes an accumulator for generating an accumulated value according to the channel number. The frequency synthesizer circuit generates the radio-frequency clock signal according to the reference clock signal and the accumulated value. The controller maintains the accumulated value of the accumulator when the portion of the frequency synthesizer circuit powers down.