Abstract:
The present inventions are related to systems and methods for data processing, and more particularly to systems and methods for priority based data processing.
Abstract:
Various embodiments of the present invention provide systems and methods for equalization. As an example, a circuit for data equalization is described that includes a 2N state detector circuit that provides a series of detected bits based upon a conditioned input, and a noise predictive filter having a plurality of taps and operable to provide at least a portion of the conditioned input. At least a first of the plurality of taps uses a first subset of the series of detected bits, and a second of the plurality of taps uses a second subset of the series of detected bits. The first subset of the detected bits includes one more bit than the second subset of the detected bits.
Abstract:
Aspects of the disclosure pertain to a system and method for providing zero gain start (ZGS) and gain acquisition based on an adaptive analog-to-digital converter (ADC) target. The adaptive ADC target is used to collect channel characteristics and based on the adaptive ADC target, an adjusted 2T amplitude target value is generated.
Abstract:
A data processing system includes an equalizer circuit operable to equalize digital data according to tap coefficients to yield equalized data, a tap coefficient adaptation circuit operable to adapt the tap coefficients based at least in part on a scaled error signal, a data detector operable to apply a data detection algorithm to the digital data to generate hard decisions and soft decisions, an error calculation circuit operable to calculate an error signal based on the equalized data and on the hard decisions, and a scaling circuit operable to scale the error signal based on the soft decisions to yield the scaled error signal.
Abstract:
Systems, methods, devices, circuits for data processing, and more particularly to data processing including adjacent track interference detection and/or characterization.
Abstract:
An apparatus includes an array reader with multiple of read heads operable to read a preamble pattern from a magnetic storage medium. A number of analog to digital converters are operable to sample an output of each of the read heads to generate digital data streams for the preamble pattern. A zero phase start calculation circuit is operable to calculate a phase offset between the digital data streams and to generate an integer phase adjustment signal and a fractional phase adjustment signal.
Abstract:
A data processing system includes a binary data detector having a hard decision output, a reliability calculator operable to calculate an error pattern reliability metric for each of a number of dominant error patterns associated with the hard decision output, and a converter operable to convert the error pattern reliability metrics to multi-level soft information.
Abstract:
A data storage system identifies analog-to-digital conversion samples with amplitude below a certain threshold. Remaining samples are grouped according to phase into one or more quadrants. A multi-coordinate with overlapping quadrants is used to further differentiate sample points. The system then computes an average phase for zero phase start estimation.
Abstract:
Systems and method relating generally to data processing, and more particularly to systems and methods for utilizing multiple data streams for data recovery from a storage device.