公开(公告)号：US11509297B2

公开(公告)日：2022-11-22

申请号：US17517493

申请日：2021-11-02

Applicant: SK hynix Inc. ,  Korea University Research and Business Foundation

Inventor： Minseop Lee ,  Hyunsu Park ,  Jincheol Sim ,  Chulwoo Kim

IPC: H03K5/156 ,  H03K5/13 ,  H03K5/00

Abstract: A duty cycle correction circuit includes a first duty cycle detecting circuit configured to detect a duty cycle of a clock signal with a first resolution; a reference clock generating circuit configured to generate a reference clock signal by adjusting a phase of the clock signal; a second duty cycle detecting circuit configured to detect a duty cycle of the clock signal with a second resolution according to the reference clock signal and the clock signal, the second resolution being finer than the first resolution; a first duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more first control signals output from the first duty cycle detecting circuit; and a second duty cycle adjusting circuit configured to adjust the duty cycle of the clock signal according to one or more second control signals output from the second duty cycle detecting circuit.

公开(公告)号：US10996807B2

公开(公告)日：2021-05-04

申请号：US16776688

申请日：2020-01-30

Applicant: KOREA UNIVERSITY RESEARCH AND BUSINESS FOUNDATION

Inventor： Chulwoo Kim

IPC: G06F3/041 ,  G06F3/044

Abstract: A display device includes a first touch panel on which a first touch sensing unit including a plurality of coils is disposed, a second touch panel on which a second touch sensing unit including a plurality of sensing nodes coupled to the plurality of coils in a coupling manner with a one-to-one correspondence, and a display panel disposed between the first and second touch panels and displays an image, and the plurality of sensing nodes is formed in a divided structure grouped into first and second node groups based on a touch event detected by the first touch sensing unit.

公开(公告)号：US09461665B1

公开(公告)日：2016-10-04

申请号：US14837049

申请日：2015-08-27

Applicant: Korea University Research and Business Foundation

Inventor： Chulwoo Kim ,  Sejin Park

IPC: H03M1/46 ,  H03M1/06

CPC classification number: H03M1/462 ,  H03M1/0607 ,  H03M1/201 ,  H03M1/468

Abstract: A Successive Approximated Register Analog-to-Digital Converter (“SARADC”) is provided that includes: a bootstrapping unit that receives and samples analog signals; and an Analog-to-Digital Conversion Unit (“ADCU”) that converts the analog signals into digital signals and outputs the digital signals. ADCU has a resolution increasing in response to an intentionally injected offset voltage. In this case, ADCU includes Capacitor Arrays (“CAs”) having: a differential structure each including reference voltage application capacitors having different capacitances and an Offset Voltage Injection Capacitor (“OVIC”); a delay cell that operates CAs in an asynchronous mode; Reference Transfer Switch Units (“RTSUs”) that apply a reference voltage to CAs; a comparator that compares output voltages of CAs; and Successive Approximated Register Logics (“SARLs”). SARLs control operations of RTSUs in response to an output signal of the comparator and perform control so that a reference voltage is applied to OVICs when the output of the comparator is abnormal.

Abstract translation: 提供了一种连续近似寄存器模数转换器（“SARADC”），其包括：自举单元，其接收和采样模拟信号; 以及将模拟信号转换为数字信号并输出​​数字信号的模数转换单元（“ADCU”）。 ADCU响应于有意注入的失调电压而具有增加的分辨率。 在这种情况下，ADCU包括具有：差分结构的电容阵列（“CA”），每个差分结构包括具有不同电容的参考电压施加电容器和偏移电压注入电容器（“OVIC”）; 以异步模式操作CA的延迟单元; 参考转换开关单元（“RTSU”），将参考电压应用于CA; 比较器，用于比较CA的输出电压; 和连续近似寄存器逻辑（“SARL”）。 SARL根据比较器的输出信号控制RTSU的操作，并执行控制，以便当比较器的输出异常时，将参考电压施加到OVIC。

公开(公告)号：US11025269B2

公开(公告)日：2021-06-01

申请号：US16871082

申请日：2020-05-11

Applicant: Korea University Research and Business Foundation

Inventor： Chulwoo Kim ,  Chae Kang Lim ,  Yo Han Choi

IPC: H03M3/00 ,  H03F3/04

Abstract: According to an exemplary embodiment, a capacitively coupled continuous-time delta-sigma modulator includes an instrumentation amplifier amplifying an input voltage to an output voltage of a predetermined magnitude, a delta-sigma modulator outputting a bit signal quantized depending on a sampling frequency based on the output voltage and to convert the bit signal into a digital-to-analog conversion voltage, and a ripple reduction loop unit generating a demodulation voltage, in which a ripple is removed from the output voltage, depending on an RRL operating frequency to feed the demodulation voltage back to the instrumentation amplifier. The RRL operating frequency is equal to the sampling frequency.

公开(公告)号：US20150010122A1

公开(公告)日：2015-01-08

申请号：US14281767

申请日：2014-05-19

Applicant: SK Hynix Inc. ,  Korea University Research and Business Foundation

Inventor： Young-Hyun Baek ,  Jun-Young Song ,  Chulwoo Kim ,  Hyun-Woo Lee

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0037 ,  H04L7/0008 ,  H04L7/033

Abstract: A system includes a transmitter including: an aligner configured to align the phases of an input clock signal and data signal; and a transmission circuit configured to generate a transmission signal of which the phase and amplitude are controlled according to the aligned clock signal and the aligned data signal. The system may also include a receiver including: a clock extraction circuit configured to extract a temporary clock signal from the transmission signal; a data extraction circuit configured to extract a temporary data signal from the transmission signal; a clock delay selector configured to generate the clock signal by delaying the temporary clock signal according to a value of the temporary data signal; and a data recovery circuit configured to sample the temporary data signal according to the clock signal outputted from the clock delay selector and output a data signal.

Abstract translation: 一种系统包括：发射机，包括：对准器，被配置为对准输入时钟信号和数据信号的相位; 以及发送电路，被配置为根据对准的时钟信号和对准的数据信号生成相位和幅度被控制的发送信号。 该系统还可以包括：接收机，包括：时钟提取电路，被配置为从传输信号中提取临时时钟信号; 数据提取电路，被配置为从所述发送信号中提取临时数据信号; 时钟延迟选择器，被配置为通过根据临时数据信号的值延迟临时时钟信号来产生时钟信号; 以及数据恢复电路，被配置为根据从时钟延迟选择器输出的时钟信号对临时数据信号进行采样，并输出数据信号。