公开(公告)号：US11025269B2

公开(公告)日：2021-06-01

申请号：US16871082

申请日：2020-05-11

Applicant: Korea University Research and Business Foundation

Inventor： Chulwoo Kim ,  Chae Kang Lim ,  Yo Han Choi

IPC: H03M3/00 ,  H03F3/04

Abstract: According to an exemplary embodiment, a capacitively coupled continuous-time delta-sigma modulator includes an instrumentation amplifier amplifying an input voltage to an output voltage of a predetermined magnitude, a delta-sigma modulator outputting a bit signal quantized depending on a sampling frequency based on the output voltage and to convert the bit signal into a digital-to-analog conversion voltage, and a ripple reduction loop unit generating a demodulation voltage, in which a ripple is removed from the output voltage, depending on an RRL operating frequency to feed the demodulation voltage back to the instrumentation amplifier. The RRL operating frequency is equal to the sampling frequency.