公开(公告)号：US09110723B2

公开(公告)日：2015-08-18

申请号：US13997630

申请日：2013-03-13

Applicant: INTEL CORPORATION

Inventor： Jason M. Agron ,  Koichi Yamada

IPC: G06F9/46 ,  G06F9/50 ,  G06F1/32

CPC classification number: G06F9/5027 ,  G06F1/3203 ,  G06F1/3206 ,  G06F1/329 ,  G06F9/505 ,  G06F9/5094 ,  G06F2209/5017 ,  Y02D10/22 ,  Y02D10/24

Abstract: Embodiments of techniques and systems associated with binary translation (BT) in computing systems are disclosed. In some embodiments, a BT task to be processed may be identified. The BT task may be associated with a set of code and may be identified during execution of the set of code on a first processing core of the computing device. The BT task may be queued in a queue accessible to a second processing core of the computing device, the second processing core being different from the first processing core. In response to a determination that the second processing core is in an idle state or has received an instruction through an operating system to enter an idle state, at least some of the BT task may be processed using the second processing core. Other embodiments may be described and/or claimed.

Abstract translation: 公开了与计算系统中的二进制翻译（BT）相关联的技术和系统的实施例。 在一些实施例中，可以识别待处理的BT任务。 BT任务可以与一组代码相关联，并且可以在计算设备的第一处理核心处的该代码集的执行期间被识别。 BT任务可以排队在计算设备的第二处理核心可访问的队列中，第二处理核心与第一处理核心不同。 响应于第二处理核心处于空闲状态或已经通过操作系统接收到进入空闲状态的指令的确定，可以使用第二处理核来处理BT任务中的至少一些。 可以描述和/或要求保护其他实施例。

公开(公告)号：US20230315501A1

公开(公告)日：2023-10-05

申请号：US17711770

申请日：2022-04-01

Applicant: Intel Corporation

Inventor： Sebastian Winkel ,  Rangeen Basu Roy Chowdhury ,  Matthew C. Merten ,  Jason M. Agron ,  Tyler N. Sondag ,  Gregory A. Woods

IPC: G06F9/455

CPC classification number: G06F9/4552 ,  G06F9/45525

Abstract: Systems, methods, and devices for original code emulation for performance monitoring is provided. A system may memory to store instructions. A processor may implement an instruction converter in hardware or software to convert the instructions to translated code. Specifically, the instruction converter receives the instructions and translates the stored instructions into the translated code that includes one or more indexed instructions. The one or more indexed instructions include a field indicating a number of branches in the stored instructions that are taken in the translated code.

公开(公告)号：US11372775B2

公开(公告)日：2022-06-28

申请号：US16777063

申请日：2020-01-30

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Jason M. Agron ,  Cristiano Pereira ,  Rangeen Basu Roy Chowdhury

IPC: G06F12/10 ,  G06F12/12 ,  G06F12/1027 ,  G06F12/1009 ,  G06F9/32 ,  G06F12/0831 ,  G06F9/38 ,  G06F8/00 ,  G06F12/02

Abstract: A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.

公开(公告)号：US20200174944A1

公开(公告)日：2020-06-04

申请号：US16777063

申请日：2020-01-30

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Jason M. Agron ,  Cristiano Pereira ,  Rangeen Basu Roy Chowdhury

IPC: G06F12/1027 ,  G06F9/38 ,  G06F12/0831 ,  G06F9/32 ,  G06F12/12 ,  G06F12/1009 ,  G06F12/02 ,  G06F8/00

Abstract: A processor comprising an instruction execution circuit to execute a second code stored at a second address of a memory, wherein the second code is translated from a first code stored at a first address of the memory and a translation table (TT) controller coupled to a translation table to store a TT entry comprising a mapping between the first address and the second address and an attribute field comprising an attribute value associated with execution of the second code, wherein the TT controller is to monitor execution of the second code by the instruction execution circuit and update, based on a performance metric of the execution, the attribute value of the TT entry.

公开(公告)号：US20190179766A1

公开(公告)日：2019-06-13

申请号：US15839310

申请日：2017-12-12

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Jason M. Agron ,  Cristiano Pereira ,  Glenn Hinton ,  Sebastian Winkel ,  Rangeen Basu Roy Chowdhury

IPC: G06F12/1009 ,  G06F12/1027 ,  G06F9/30

Abstract: A processor comprising an instruction execution circuit to execute a translated code generated based on a received code and a translation table (TT) controller circuit coupled to a translation table comprising a plurality of address mappings, wherein the TT controller circuit is to identify a trigger event associated with a physical memory page, determine, based on an identifier of the physical memory page, an entry in a manifest table, the entry comprising an address mapping between a first memory address within an address range comprising the physical memory page and a second memory address, and store the address mapping to the translation table.

公开(公告)号：US10114643B2

公开(公告)日：2018-10-30

申请号：US14129531

申请日：2013-05-23

Applicant: INTEL CORPORATION

Inventor： Koichi Yamada ,  Palanivelra Shanmugavelayutham ,  Arvind Krishnaswamy ,  Jason M. Agron ,  Jiwei Lu

IPC: G06F9/30 ,  G06F21/54 ,  G06F12/08 ,  G06F12/0875

Abstract: Various embodiments are generally directed to techniques to detect a return-oriented programming (ROP) attack by verifying target addresses of branch instructions during execution. An apparatus includes a processor component, and a comparison component for execution by the processor component to determine whether there is a matching valid target address for a target address of a branch instruction associated with a translated portion of a routine in a table comprising valid target addresses. Other embodiments are described and claimed.

公开(公告)号：US09996356B2

公开(公告)日：2018-06-12

申请号：US14998299

申请日：2015-12-26

Applicant: Intel Corporation

Inventor： Vineeth Mekkat ,  Oleg Margulis ,  Jason M. Agron ,  Ethan Schuchman ,  Sebastian Winkel ,  Youfeng Wu ,  Gisle Dankel

IPC: G06F9/30 ,  G06F9/38

CPC classification number: G06F9/30185 ,  G06F9/3826 ,  G06F9/3834 ,  G06F9/3838 ,  G06F9/3865

Abstract: Apparatus and method for detecting and recovering from incorrect memory dependence speculation in an out-of-order processor are described herein. For example, one embodiment of a method comprises: executing a first load instruction; detecting when the first load instruction experiences a bad store-to-load forwarding event during execution; tracking the occurrences of bad store-to-load forwarding event experienced by the first load instruction during execution; controlling enablement of an S-bit in the first load instruction based on the tracked occurrences; generating a plurality of load operations responsive to an enabled S-bit in first load instruction, wherein execution of the plurality of load operations produces a result equivalent to that from the execution of the first load instruction.

公开(公告)号：US09823938B2

公开(公告)日：2017-11-21

申请号：US14742908

申请日：2015-06-18

Applicant: Intel Corporation

Inventor： Girish Venkatasubramanian ,  Jamison D. Collins ,  Jason M. Agron ,  Polychronis Xekalakis

IPC: G06F9/45 ,  G06F9/455 ,  G06F9/30

CPC classification number: G06F9/45516 ,  G06F9/30 ,  G06F11/00

Abstract: In one embodiment, a processor includes a front end unit to fetch and decode an instruction. The front end unit includes a first random number generator to generate a random value responsive to a profileable event associated with the instruction. The processor further includes a profile logic to collect profile information associated with the instruction responsive to a sample signal, where the sample signal is based on at least a portion of the random value. Other embodiments are described and claimed.