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公开(公告)号:US20150221748A1
公开(公告)日:2015-08-06
申请号:US14689578
申请日:2015-04-17
IPC分类号: H01L29/66 , H01L29/423 , H01L21/306 , H01L29/40 , H01L29/20 , H01L21/02
CPC分类号: H01L29/66462 , H01L21/0254 , H01L21/30604 , H01L29/155 , H01L29/2003 , H01L29/407 , H01L29/41725 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/778 , H01L29/7783
摘要: A method of manufacturing a transistor device includes forming a semiconductor heterostructure including a plurality of alternating two-dimensional electron gasses (2DEGs) and two-dimensional hole gasses (2DHGs) extending in parallel at different depths in the semiconductor heterostructure, the 2DEGs forming current channels of the transistor device, forming a source extending into the semiconductor heterostructure in contact with the 2DEGs at a first end of the current channels, forming a drain extending into the semiconductor heterostructure in contact with the 2DEGs at an opposing second end of the current channels, and forming a plurality of spaced apart gate structures extending into the semiconductor heterostructure and including an electrically conductive material separated from the surrounding semiconductor heterostructure by an insulating material.
摘要翻译: 一种制造晶体管器件的方法包括形成半导体异质结构,其包括在半导体异质结构中以不同深度平行延伸的多个交替的二维电子气体(2DEG)和二维空穴(2DHG),2DEG形成电流通道 形成在电流通道的第一端处延伸到与2DEG接触的半导体异质结构中的源,形成在当前通道的相对的第二端处延伸到与2DEG接触的半导体异质结构中的漏极, 以及形成延伸到半导体异质结构中的多个间隔开的栅极结构,并且包括通过绝缘材料与周围的半导体异质结构分离的导电材料。
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公开(公告)号:US20140054697A1
公开(公告)日:2014-02-27
申请号:US14068583
申请日:2013-10-31
发明人: Oliver Haeberlen
IPC分类号: H01L29/78 , H01L21/283 , H01L29/40
CPC分类号: H01L29/7825 , H01L21/283 , H01L21/823437 , H01L21/823487 , H01L27/088 , H01L29/407
摘要: A semiconductor device with a field electrode and method. One embodiment provides a controllable semiconductor device including a control electrode for controlling the semiconductor device and a field electrode. The field electrode includes a number of longish segments which extend in a first lateral direction and which run substantially parallel to one another. The control electrode includes a number of longish segments extending in a second lateral direction and running substantially parallel to one another, wherein the first lateral direction is different from the second lateral direction.
摘要翻译: 一种具有场电极和方法的半导体器件。 一个实施例提供了一种可控制的半导体器件,其包括用于控制半导体器件的控制电极和场电极。 场电极包括在第一横向方向上延伸并且基本上彼此平行地延伸的多个较长的段。 控制电极包括在第二横向方向上延伸并基本上彼此平行地延伸的多个长条,其中第一横向方向与第二横向方向不同。
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公开(公告)号:US20130228858A1
公开(公告)日:2013-09-05
申请号:US13852127
申请日:2013-03-28
发明人: Oliver Haeberlen , Joachim Krumrey , Franz Hirler , Walter Rieger
IPC分类号: H01L29/78
CPC分类号: H01L29/7813 , H01L21/26586 , H01L27/0629 , H01L29/0623 , H01L29/0834 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/404 , H01L29/407 , H01L29/41766 , H01L29/42368 , H01L29/495 , H01L29/4966 , H01L29/66727 , H01L29/66734 , H01L29/7397 , H01L29/7803 , H01L29/7805
摘要: A semiconductor device includes a source metallization, a source region of a first conductivity type in contact with the source metallization, a body region of a second conductivity type which is adjacent to the source region. The semiconductor device further includes a first field-effect structure including a first insulated gate electrode and a second field-effect structure including a second insulated gate electrode which is electrically connected to the source metallization. The capacitance per unit area between the second insulated gate electrode and the body region is larger than the capacitance per unit area between the first insulated gate electrode and the body region.
摘要翻译: 半导体器件包括源极金属化,与源极金属化接触的第一导电类型的源极区域,与源极区域相邻的第二导电类型的主体区域。 半导体器件还包括第一场效应结构,其包括第一绝缘栅电极和第二场效应结构,第二场效应结构包括与源极金属化电连接的第二绝缘栅电极。 第二绝缘栅电极和体区之间的每单位面积的电容大于第一绝缘栅极与体区之间的每单位面积的电容。
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公开(公告)号:US20230163209A1
公开(公告)日:2023-05-25
申请号:US18100620
申请日:2023-01-24
发明人: Gerhard Prechtl , Oliver Haeberlen
IPC分类号: H01L29/778 , H01L23/00 , H01L29/205 , H01L29/66
CPC分类号: H01L29/7787 , H01L29/7786 , H01L23/564 , H01L29/205 , H01L29/66462 , H01L29/402
摘要: A semiconductor device includes: a device formed in a III-V semiconductor body; metal layer(s) above the III-V semiconductor body; an interlayer dielectric adjacent each metal layer; vias electrically connecting each metal layer to the device formed in the III-V semiconductor body; a passivation layer touching and being supported by a top surface of the III-V semiconductor body, the lowermost interlayer dielectric touching and being supported by a top surface of the passivation layer, the passivation layer being an ineffective barrier against diffusion of water, water ions, sodium ions and potassium ions into the III-V semiconductor body; and a barrier interposed between a first oxide layer and a second oxide layer of the lowermost interlayer dielectric. The barrier is configured to prevent water, water ions, sodium ions and potassium ions from diffusing into the first oxide layer of the lowermost interlayer dielectric and which is immediately below the barrier.
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公开(公告)号:US11349012B2
公开(公告)日:2022-05-31
申请号:US16837506
申请日:2020-04-01
IPC分类号: H01L29/66 , H01L29/20 , H01L29/423 , H01L29/778
摘要: In an embodiment, a Group III nitride-based transistor device, includes a first. Group III nitride barrier layer arranged on a Group III nitride channel layer, the first Group III nitride barrier layer and the Group III nitride channel layer having differing bandgaps and forming a heterojunction capable of supporting a two-dimensional charge gas. A source, a gate and a drain are on an upper surface of the first Group III nitride barrier layer. A gate recess extends from the upper surface of the first. Group III nitride barrier layer into the first Group III nitride barrier layer. A p-doped Group III nitride material arranged in the gate recess has a first extension extending on the upper surface of the first Group III nitride barrier layer towards the drain. The first extension has a length ld, and 0 nm≤ld≤200 nm.
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公开(公告)号:US11004966B2
公开(公告)日:2021-05-11
申请号:US14708736
申请日:2015-05-11
发明人: Oliver Haeberlen , Walter Rieger
IPC分类号: H01L29/66 , H01L29/778 , H01L29/20 , H01L29/423 , H01L27/085 , H01L27/06 , H01L29/201 , H01L29/205 , H01L29/417 , H01L29/10 , H01L29/43
摘要: A semiconductor device is described. In one embodiment, the device includes a Group-III nitride channel layer and a Group-III nitride barrier layer on the Group-III nitride channel layer, wherein the Group-III nitride barrier layer includes a first portion and a second portion, the first portion having a thickness less than the second portion. A p-doped Group-III nitride gate layer section is arranged at least on the first portion of the Group-III nitride barrier layer and a gate contact formed on the p-doped Group-III nitride gate layer.
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公开(公告)号:US10199216B2
公开(公告)日:2019-02-05
申请号:US14757896
申请日:2015-12-24
IPC分类号: H01L21/02 , H01L31/18 , C30B33/08 , C30B15/34 , C30B29/40 , H01L21/304 , H01L21/306 , H01L21/308 , H01L29/06 , H01L29/20
摘要: In an embodiment, a method includes treating an edge region of a wafer including a substrate having an upper surface and one or more epitaxial Group III nitride layers arranged on the upper surface of the substrate, so as to remove material including at least one Group III element from the edge region.
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公开(公告)号:US10153362B2
公开(公告)日:2018-12-11
申请号:US15336036
申请日:2016-10-27
IPC分类号: H01L29/778 , H01L29/08 , H01L29/10 , H01L29/20 , H01L29/205 , H01L29/40 , H01L29/423
摘要: In an embodiment, a semiconductor device includes an enhancement mode Group III-nitride-based High Electron Mobility Transistor (HEMT) including a drain, a gate, a barrier layer, a channel layer, a barrier layer arranged on the channel layer, and a heterojunction formed between the barrier layer and the channel layer and capable of supporting a two-dimensional electron gas (2DEG). At least one of a thickness and a composition of the barrier layer is configured to decrease a 2DEG density in a channel region compared with a 2DEG density outside of the channel region, wherein the channel region is arranged under the gate and extends a distance d beyond a drain-sided gate edge.
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公开(公告)号:US10038085B2
公开(公告)日:2018-07-31
申请号:US14991517
申请日:2016-01-08
IPC分类号: H01L29/778 , H01L29/66 , H01L21/66 , H01L29/20 , H01L29/205
CPC分类号: H01L29/7784 , H01L22/26 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/66462 , H01L29/7783
摘要: A method includes providing a heterostructure body with a buffer region, and a barrier region disposed on the buffer region, and forming a gate structure for controlling the channel on the heterostructure body, the gate structure having a doped semiconductor region disposed on the heterostructure body, an interlayer disposed on the doped semiconductor region, and a gate electrode disposed on the interlayer. Forming the gate structure includes controlling a doping concentration of the doped semiconductor region such that a portion of the channel adjacent the gate structure is non-conductive at zero gate bias, and controlling electrical and geometrical characteristics of the interlayer based upon a relationship between the electrical and geometrical characteristics of the interlayer and corresponding effects on a static threshold voltage and a dynamic threshold voltage shift of the semiconductor device.
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公开(公告)号:US09837522B2
公开(公告)日:2017-12-05
申请号:US14929856
申请日:2015-11-02
IPC分类号: H01L29/778 , H01L29/20 , H01L29/205 , H01L29/423 , H01L29/10
CPC分类号: H01L29/7787 , H01L29/1029 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/42312 , H01L29/42316 , H01L29/7783
摘要: There are disclosed herein various implementations of a III-Nitride bidirectional device. Such a bidirectional device includes a substrate, a back channel layer situated over the substrate, and a device channel layer and a device barrier layer situated over the back channel layer. The device channel layer and the device barrier layer are configured to produce a device two-dimensional electron gas (2DEG). In addition, the III-Nitride bidirectional device includes first and second gates formed on respective first and second depletion segments situated over the device barrier layer. The III-Nitride bidirectional device also includes a back barrier situated between the back channel layer and the device channel layer. A polarization of the back channel layer of the III-Nitride bidirectional device is substantially equal to a polarization of the device channel layer.
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