公开(公告)号：US10964664B2

公开(公告)日：2021-03-30

申请号：US16386261

申请日：2019-04-17

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Chandrasekhar Mandalapu ,  Gaius Gillman Fountain, Jr. ,  Guilian Gao

IPC: H01L21/683 ,  H01L21/02 ,  H01L21/78 ,  H01L21/762 ,  H01L23/00

Abstract: Devices and techniques include process steps for preparing various microelectronic components for bonding, such as for direct bonding without adhesive. The processes include providing a first bonding surface on a first surface of the microelectronic components, bonding a handle to the prepared first bonding surface, and processing a second surface of the microelectronic components while the microelectronic components are gripped at the handle. In some embodiments, the processes include removing the handle from the first bonding surface, and directly bonding the microelectronic components at the first bonding surface to other microelectronic components.

公开(公告)号：US10727219B2

公开(公告)日：2020-07-28

申请号：US16262489

申请日：2019-01-30

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Guilian Gao ,  Gaius Gillman Fountain, Jr.

IPC: H01L21/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L21/18

Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.

公开(公告)号：US11355404B2

公开(公告)日：2022-06-07

申请号：US16845913

申请日：2020-04-10

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Guilian Gao ,  Laura Wills Mirkarimi ,  Gaius Gillman Fountain, Jr.

IPC: H01L21/66 ,  H01L21/768 ,  H01L23/532 ,  H01L23/538 ,  H01L23/522

Abstract: Mitigating surface damage of probe pads in preparation for direct bonding of a substrate is provided. Methods and layer structures prepare a semiconductor substrate for direct bonding processes by restoring a flat direct-bonding surface after disruption of probe pad surfaces during test probing. An example method fills a sequence of metals and oxides over the disrupted probe pad surfaces and builds out a dielectric surface and interconnects for hybrid bonding. The interconnects may be connected to the probe pads, and/or to other electrical contacts of the substrate. A layer structure is described for increasing the yield and reliability of the resulting direct bonding process. Another example process builds the probe pads on a next-to-last metallization layer and then applies a direct bonding dielectric layer and damascene process without increasing the count of mask layers. Another example process and related layer structure recesses the probe pads to a lower metallization layer and allows recess cavities over the probe pads.

公开(公告)号：US11296053B2

公开(公告)日：2022-04-05

申请号：US16911360

申请日：2020-06-24

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Cyprian Emeka Uzoh ,  Rajesh Katkar ,  Thomas Workman ,  Guilian Gao ,  Gaius Gillman Fountain, Jr. ,  Laura Wills Mirkarimi ,  Belgacem Haba ,  Gabriel Z. Guevara ,  Joy Watanabe

IPC: H01L25/065 ,  H01L23/00 ,  H01L23/31 ,  H01L21/56

Abstract: Direct bonded stack structures for increased reliability and improved yields in microelectronics are provided. Structural features and stack configurations are provided for memory modules and 3DICs to reduce defects in vertically stacked dies. Example processes alleviate warpage stresses between a thicker top die and direct bonded dies beneath it, for example. An etched surface on the top die may relieve warpage stresses. An example stack may include a compliant layer between dies. Another stack configuration replaces the top die with a layer of molding material to circumvent warpage stresses. An array of cavities on a bonding surface can alleviate stress forces. One or more stress balancing layers may also be created on a side of the top die or between other dies to alleviate or counter warpage. Rounding of edges can prevent stresses and pressure forces from being destructively transmitted through die and substrate layers. These measures may be applied together or in combinations in a single package.

公开(公告)号：US11289372B2

公开(公告)日：2022-03-29

申请号：US17330895

申请日：2021-05-26

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Paul M. Enquist ,  Gaius Gillman Fountain, Jr. ,  Qin-Yi Tong

IPC: H01L21/768 ,  H01L23/48 ,  H01L23/00 ,  H01L25/065 ,  H01L25/00 ,  H01L27/06

Abstract: A method of three-dimensionally integrating elements such as singulated die or wafers and an integrated structure having connected elements such as singulated dies or wafers. Either or both of the die and wafer may have semiconductor devices formed therein. A first element having a first contact structure is bonded to a second element having a second contact structure. First and second contact structures can be exposed at bonding and electrically interconnected as a result of the bonding. A via may be etched and filled after bonding to expose and form an electrical interconnect to interconnected first and second contact structures and provide electrical access to this interconnect from a surface.

公开(公告)号：US11004757B2

公开(公告)日：2021-05-11

申请号：US16235585

申请日：2018-12-28

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Rajesh Katkar ,  Laura Wills Mirkarimi ,  Bongsub Lee ,  Gaius Gillman Fountain, Jr. ,  Cyprian Emeka Uzoh

IPC: H01L23/10 ,  H01L23/00 ,  H01L21/768

Abstract: A bonded structure is disclosed. The bonded structure includes a first element and a second element that is bonded to the first element along a bonding interface. The bonding interface has an elongate conductive interface feature and a nonconductive interface feature. The bonded structure also includes an integrated device that is coupled to or formed with the first element or the second element. The elongate conductive interface feature has a recess through a portion of a thickness of the elongate conductive interface feature. A portion of the nonconductive interface feature is disposed in the recess.

公开(公告)号：US10529634B2

公开(公告)日：2020-01-07

申请号：US15837941

申请日：2017-12-11

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Javier A. Delacruz ,  Paul M. Enquist ,  Gaius Gillman Fountain, Jr. ,  Ilyas Mohammed

IPC: H01L21/66 ,  H01L23/00

Abstract: Representative implementations of devices and techniques provide a temporary access point (e.g., for testing, programming, etc.) for a targeted interconnect located among multiple finely spaced interconnects on a surface of a microelectronic component. One or more sacrificial layers are disposed on the surface of the microelectronic component, overlaying the multiple interconnects. An insulating layer is disposed between a conductive layer and the surface, and includes a conductive via through the insulating layer that electrically couples the conductive layer to the target interconnect. The sacrificial layers are configured to be removed after the target interconnect has been accessed, without damaging the surface of the microelectronic component.

公开(公告)号：US10446532B2

公开(公告)日：2019-10-15

申请号：US15389157

申请日：2016-12-22

Applicant: INVENSAS BONDING TECHNOLOGIES, INC.

Inventor： Cyprian Emeka Uzoh ,  Paul M. Enquist ,  Gaius Gillman Fountain, Jr.

IPC: H01L21/683 ,  H01L25/00 ,  H01L21/78 ,  H01L21/66 ,  H01L25/10

Abstract: Systems and methods for efficient transfer of elements are disclosed. A film which supports a plurality of diced integrated device dies can be provided. The plurality of diced integrated device dies can be disposed adjacent one another along a surface of the film. The film can be positioned adjacent the support structure such that the surface of the film faces a support surface of the support structure. The film can be selectively positioned laterally relative to the support structure such that a selected first die is aligned with a first location of the support structure. A force can be applied in a direction nonparallel to the surface of the film to cause the selected first die to be directly transferred from the film to the support structure.

公开(公告)号：US11158573B2

公开(公告)日：2021-10-26

申请号：US16657696

申请日：2019-10-18

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Cyprian Emeka Uzoh ,  Gaius Gillman Fountain, Jr. ,  Jeremy Alfred Theil

IPC: H01L23/48 ,  H01L23/522 ,  H01L23/00 ,  H01L23/29 ,  H01L23/31

Abstract: Representative techniques and devices, including process steps may be employed to mitigate undesired dishing in conductive interconnect structures and erosion of dielectric bonding surfaces. For example, an embedded layer may be added to the dished or eroded surface to eliminate unwanted dishing or voids and to form a planar bonding surface. Additional techniques and devices, including process steps may be employed to form desired openings in conductive interconnect structures, where the openings can have a predetermined or desired volume relative to the volume of conductive material of the interconnect structures. Each of these techniques, devices, and processes can provide for the use of larger diameter, larger volume, or mixed-sized conductive interconnect structures at the bonding surface of bonded dies and wafers.

公开(公告)号：US11037919B2

公开(公告)日：2021-06-15

申请号：US16919989

申请日：2020-07-02

Applicant: Invensas Bonding Technologies, Inc.

Inventor： Cyprian Emeka Uzoh ,  Laura Wills Mirkarimi ,  Guilian Gao ,  Gaius Gillman Fountain, Jr.

IPC: H01L21/00 ,  H01L25/00 ,  H01L25/065 ,  H01L23/00 ,  H01L21/78 ,  H01L21/683 ,  H01L21/18

Abstract: Representative techniques provide process steps for forming a microelectronic assembly, including preparing microelectronic components such as dies, wafers, substrates, and the like, for bonding. One or more surfaces of the microelectronic components are formed and prepared as bonding surfaces. The microelectronic components are stacked and bonded without adhesive at the prepared bonding surfaces.