公开(公告)号：US09785551B2

公开(公告)日：2017-10-10

申请号：US14953320

申请日：2015-11-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Licheng Chen ,  Zehan Cui

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0284 ,  G06F13/1605 ,  G06F13/1673 ,  G06F2212/1044 ,  G06F2212/2532

Abstract: The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.

公开(公告)号：US20160085670A1

公开(公告)日：2016-03-24

申请号：US14953320

申请日：2015-11-28

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Licheng Chen ,  Zehan Cui

IPC: G06F12/02 ,  G06F13/16

CPC classification number: G06F12/0284 ,  G06F13/1605 ,  G06F13/1673 ,  G06F2212/1044 ,  G06F2212/2532

Abstract: The present invention discloses a memory access method, a buffer scheduler, and a memory module, which can support multiple application scenarios without changing the memory module or a memory chip. The method includes: receiving an operation request message for memory access data, where the operation request message includes tag information of the memory access data, operation information of the memory access data, and a memory address of the memory access data; and performing, according to at least one of the tag information of the memory access data, a memory address of the memory access data, and the operation information of the memory access data, an operation on the tag of the memory access data and/or the memory access data stored in the memory module. The present invention is applicable to the computer field.

Abstract translation: 本发明公开了一种存储器访问方法，缓冲器调度器和存储器模块，其可以在不改变存储器模块或存储器芯片的情况下支持多种应用场景。 该方法包括：接收用于存储器访问数据的操作请求消息，其中操作请求消息包括存储器访问数据的标签信息，存储器访问数据的操作信息和存储器访问数据的存储器地址; 并且根据存储器访问数据的标签信息，存储器访问数据的存储器地址和存储器访问数据的操作信息中的至少一个来执行对存储器访问数据的标签的操作和/或 存储器存储数据存储在存储器模块中。 本发明可应用于计算机领域。

公开(公告)号：US20150220135A1

公开(公告)日：2015-08-06

申请号：US14685272

申请日：2015-04-13

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Yuan Ruan

IPC: G06F1/32

CPC classification number: G06F1/3225 ,  G06F1/3275 ,  G06F3/0625 ,  G06F3/0647 ,  G06F3/068 ,  G06F9/5016 ,  G06F9/5094 ,  G06F12/0638 ,  G06F2212/1028 ,  G06F2212/205 ,  G06F2212/251 ,  Y02D10/13 ,  Y02D10/14 ,  Y02D10/154 ,  Y02D10/22 ,  Y02D50/20

Abstract: A method for reducing power consumption of a memory system and a memory controller are provided. The method for reducing power consumption of a memory system includes: determining whether a dynamic random access memory DRAM memory module with a low access frequency exists in a memory system; when a DRAM memory module with a low access frequency exists, transfer, according to a size of a working set in the memory system, page data that does not belong to the working set to a non-volatile memory NVM memory module, where the page data that does not belong to the working set is page data that does not need to be accessed when a process runs within preset time.

Abstract translation: 提供了一种用于降低存储器系统和存储器控制器的功耗的方法。 用于降低存储器系统的功耗的方法包括：确定存储系统中是否存在具有低存取频率的动态随机存取存储器DRAM存储器模块; 当存在具有低访问频率的DRAM存储器模块时，根据存储器系统中的工作集的大小将不属于工作集的页面数据传送到非易失性存储器NVM存储器模块，其中页面 不属于工作集的数据是当一个进程在预设时间内运行时不需要访问的页面数据。

公开(公告)号：US10831677B2

公开(公告)日：2020-11-10

申请号：US16028265

申请日：2018-07-05

Applicant: Huawei Technologies Co., Ltd.

Inventor： Jun Xu ,  Yongbing Huang ,  Yuangang Wang

IPC: G06F12/121 ,  G06F12/122 ,  G06F12/0804 ,  G06F12/0871 ,  G06F3/06

Abstract: A cache management method, a cache controller, and a computer system are provided. In the method, the cache controller obtains an operation instruction; when a destination address in the operation instruction hits no cache line cache line in a cache of the computer system, and the cache includes no idle cache line, the cache controller selects a to-be-replaced cache line from a replacement set, where the replacement set includes at least two cache lines; and the cache controller eliminates the to-be-replaced cache line from the cache, and stores, in the cache, a cache line obtained from the destination address. According to the cache management method, system overheads of cache line replacement can be reduced, and cache line replacement efficiency can be improved.

公开(公告)号：US10439736B2

公开(公告)日：2019-10-08

申请号：US15846139

申请日：2017-12-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Tongtong Cao ,  Qinfen Hao ,  Shuncheng Pan

IPC: G06F15/80 ,  H04B10/80 ,  G06F12/0831 ,  H04Q11/00

Abstract: An optical switch control method and an apparatus are disclosed, to reduce impact on access performance by time overheads of optical link switching. The method includes: receiving an optical link establishment request sent by a computation node; determining whether the first optical link that needs to be established conflicts with the existing optical link; and if the first optical link that needs to be established conflicts with the existing optical link, determining whether to allow establishment of the first optical link, and establishing the first optical link if the establishment of the first optical link is allowed; or establishing the first optical link if the first optical link that needs to be established does not conflict with the existing optical link.

公开(公告)号：US10007599B2

公开(公告)日：2018-06-26

申请号：US15373888

申请日：2016-12-09

Applicant: HUAWEI TECHNOLOGIES CO.,LTD.

Inventor： Zehan Cui ,  Mingyu Chen ,  Yongbing Huang

IPC: G06F12/00 ,  G06F12/02 ,  G11C11/406 ,  G11C11/4091 ,  G11C11/4096 ,  G06F3/06 ,  G06F12/1009

CPC classification number: G06F12/023 ,  G06F3/061 ,  G06F3/0659 ,  G06F3/0665 ,  G06F3/0673 ,  G06F12/1009 ,  G06F2212/1016 ,  G06F2212/152 ,  G06F2212/20 ,  G06F2212/657 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4091 ,  G11C11/4096

Abstract: A method for refreshing a dynamic random access memory DRAM and a computer system are provided. When an address of a refresh unit in a DRAM and refresh information of the refresh unit are acquired, the address of the refresh unit and the refresh information of the refresh unit are encapsulated as a DRAM access request, where the refresh unit is storage space on which one time of refresh is performed in the DRAM, and the refresh information of the refresh unit includes a refresh cycle of the refresh unit. Then, the address and the refresh information of the refresh unit are written into refresh data space using the DRAM access request, where the refresh data space is storage space that is preset in the DRAM and that is used for storing an address of at least one refresh unit and refresh information of the at least one refresh unit.

公开(公告)号：US20180109327A1

公开(公告)日：2018-04-19

申请号：US15846139

申请日：2017-12-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Tongtong Cao ,  Qinfen Hao ,  Shuncheng Pan

IPC: H04B10/80 ,  G06F15/80 ,  G06F12/0831 ,  H04Q11/00

CPC classification number: H04B10/801 ,  G06F12/0833 ,  G06F15/80 ,  H04Q11/00 ,  H04Q11/0062

Abstract: An optical switch control method and an apparatus are disclosed, to reduce impact on access performance by time overheads of optical link switching. The method includes: receiving an optical link establishment request sent by a computation node; determining whether the first optical link that needs to be established conflicts with the existing optical link; and if the first optical link that needs to be established conflicts with the existing optical link, determining whether to allow establishment of the first optical link, and establishing the first optical link if the establishment of the first optical link is allowed; or establishing the first optical link if the first optical link that needs to be established does not conflict with the existing optical link.

公开(公告)号：US20180053569A1

公开(公告)日：2018-02-22

申请号：US15802781

申请日：2017-11-03

Applicant: Huawei Technologies Co., Ltd.

Inventor： Shihai Xiao ,  Yongbing Huang ,  Rui He

IPC: G11C29/00 ,  G11C11/4091 ,  G11C11/406

CPC classification number: G11C29/783 ,  G11C11/403 ,  G11C11/406 ,  G11C11/40607 ,  G11C11/40611 ,  G11C11/40618 ,  G11C11/40622 ,  G11C11/4091

Abstract: A dynamic random access memory (DRAM) refresh method in which a to-be-refreshed area in a refresh block is specified in a refresh instruction is provided to refresh a specified location of a DRAM storage array. A memory controller sends a refresh instruction to a DRAM refresh apparatus. The refresh instruction includes an identifier of a to-be-refreshed block and refresh information indicating a to-be-refreshed area. The DRAM refresh apparatus generates addresses of to-be-refreshed bank rows in the to-be-refreshed block according to the identifier and the refresh information, and refresh locations corresponding to the addresses of the bank rows in the to-be-refreshed block. Therefore, a DRAM refresh time is shortened, refresh power consumption is reduced, a refresh operation is more flexible, and system resource consumption is reduced while data integrity is ensured.

公开(公告)号：US09870327B2

公开(公告)日：2018-01-16

申请号：US14335029

申请日：2014-07-18

Applicant: Huawei Technologies Co., Ltd.

Inventor： Mingyu Chen ,  Yuan Ruan ,  Zehan Cui ,  Licheng Chen ,  Yongbing Huang ,  Mingyang Chen

IPC: G06F13/16 ,  G06F13/42

CPC classification number: G06F13/1673 ,  G06F13/4239

Abstract: A message-based memory access apparatus and an access method thereof are disclosed, The message-based memory access apparatus includes: a message-based command bus, configured to transmit a message-based memory access instruction generated by the CPU to instruct a memory system to perform a corresponding operation; a message-based memory controller, configured to package a CPU request into a message packet and sent the packet to a storage module, and parse a message packet returned by the storage module and return data to the CPU; a message channel, configured to transmit a request message packet and a response message packet; and the storage module, including a buffer scheduler, and configured to receive the request packet from the message-based memory controller and process the corresponding request.

公开(公告)号：US20160335177A1

公开(公告)日：2016-11-17

申请号：US15218826

申请日：2016-07-25

Applicant: Huawei Technologies Co., Ltd.

Inventor： Yongbing Huang ,  Mingyu Chen ,  Kun Zhang

IPC: G06F12/02

CPC classification number: G06F12/023 ,  G06F11/3037 ,  G06F11/3452 ,  G06F12/0811 ,  G06F12/0848 ,  G06F12/0862 ,  G06F12/0864 ,  G06F12/0886 ,  G06F12/0895 ,  G06F2201/885 ,  G06F2212/1024 ,  G06F2212/1041 ,  G06F2212/1044 ,  G06F2212/281 ,  G06F2212/282 ,  G06F2212/601 ,  G06F2212/603 ,  G06F2212/6042 ,  G06F2212/608

Abstract: A cache management method and apparatus are disclosed, in order to improve cache resource utilization, where the method includes receiving an access request, determining data that is to be accessed and that needs to be accessed according to the access request, determining a strength level of spatial locality of the data to be accessed, and allocating, according to the strength level of the spatial locality of the data to be accessed, a cache subunit corresponding to the level to the data to be accessed, where the method is applicable to the communications field, and may used to implement cache management.

Abstract translation: 公开了一种高速缓存管理方法和装置，以便提高高速缓存资源利用率，其中该方法包括接收访问请求，根据访问请求确定要被访问并需要被访问的数据，确定 要访问的数据的空间局部性，并且根据要访问的数据的空间局部性的强度级别分配对应于要被访问的数据的级别的缓存子单元，其中该方法适用于通信 字段，并可用于实现缓存管理。