Data transmission method, device and system
    12.
    发明授权
    Data transmission method, device and system 有权
    数据传输方式,设备和系统

    公开(公告)号:US09148264B2

    公开(公告)日:2015-09-29

    申请号:US14502326

    申请日:2014-09-30

    Abstract: A data transmission method, device and system to improve reliability of a data link. When the sender side detects erroneous data, the erroneous data is discarded and a data retransmission request is sent to the sender side to ensure correctness of received data and improve reliability of the data link; and, when the sender side detects the erroneous data and a bit error rate is greater than a preset bit error rate threshold, the data link gets into auto recovery, and data transmission is resumed after the recovery succeeds, thereby avoiding an excessively high bit error rate, preventing an excessively high probability of omitted checks (the higher the bit error rate is, the higher probability of omitted checks is), and further improving reliability of the data link.

    Abstract translation: 一种提高数据链路可靠性的数据传输方法,设备和系统。 当发送方检测到错误数据时,丢弃错误数据,并向发送方发送数据重发请求,以确保接收到的数据的正确性并提高数据链路的可靠性; 并且当发送方检测到错误数据并且误码率大于预设误码率阈值时,数据链路进入自动恢复,并且在恢复成功之后恢复数据传输,从而避免了过高的位错误 速率,防止忽略检查的概率过高(误码率越高,省略检查的概率越高),并进一步提高数据链路的可靠性。

    NVME data processing method and NVME device

    公开(公告)号:US10997093B2

    公开(公告)日:2021-05-04

    申请号:US16251805

    申请日:2019-01-18

    Inventor: Sheng Chang

    Abstract: A Non-Volatile Memory Express (NVMe) data reading/writing method and an NVMe device, where in the method, a transceiver receives an NVMe command from a host into a submission queue (SQ), an SQ control circuit sends the NVMe command in the SQ to an solid state drive (SSD) controller when detecting that the SQ in an SQ cache changes, the SSD controller executes the NVMe command, writes a generated NVMe command response into a completion queue (CQ) using a CQ control circuit, and instructs, by triggering an interrupt, the host to read the CQ such that the host processes the NVMe command response in the CQ. Because both the SQ and the CQ are located in the NVMe device, a central processing unit (CPU) can directly read the NVMe command response in the CQ or directly write the NVMe command into the SQ, thereby further reducing consumption of CPU resources.

    Storage expansion apparatus and server
    16.
    发明授权
    Storage expansion apparatus and server 有权
    存储扩展设备和服务器

    公开(公告)号:US09053252B2

    公开(公告)日:2015-06-09

    申请号:US14512790

    申请日:2014-10-13

    Abstract: A storage expansion apparatus and a server, where the storage expansion apparatus includes a quick path interconnect (QPI) interface module, which communicates with a central processing unit (CPU) through a QPI bus; a peripheral component interconnect express (PCIe) interface module, which communicates with the CPU through a PCIe bus; an interface selecting module, connected to the QPI interface module and the PCIe interface module separately; a home agent (HA) module, connected to the interface selecting module; and a memory controller engine (MCEng) module, connected to the HA module and the interface selecting module separately. The storage expansion apparatus may serve as a CPU memory capacity expansion device, and may also serve as storage expansion hardware of storage input and output (TO).

    Abstract translation: 一种存储扩展装置和服务器,其中存储扩展装置包括通过QPI总线与中央处理单元(CPU)通信的快速路径互连(QPI)接口模块; 外围组件互连快速(PCIe)接口模块,其通过PCIe总线与CPU通信; 接口选择模块,分别连接到QPI接口模块和PCIe接口模块; 连接到接口选择模块的归属代理(HA)模块; 以及分别连接到HA模块和接口选择模块的存储器控​​制器引擎(MCEng)模块。 存储扩展装置可以用作CPU存储器容量扩展装置,并且还可以用作存储输入和输出(TO)的存储扩展硬件。

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