公开(公告)号：US6078191A

公开(公告)日：2000-06-20

申请号：US38728

申请日：1998-03-10

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

公开(公告)号：US5989943A

公开(公告)日：1999-11-23

申请号：US447969

申请日：1989-12-08

Applicant: Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

Inventor： Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10 ,  H01L21/28

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

公开(公告)号：US5477167A

公开(公告)日：1995-12-19

申请号：US379061

申请日：1995-01-27

Applicant: Hua-Thye Chua

Inventor： Hua-Thye Chua

IPC: G11C17/18 ,  H03K19/177

CPC classification number: H03K19/17776 ,  G11C17/18 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17792

Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

Abstract translation: 随着处理技术的进步，可编程ASIC架构允许与设备的其他部分一起减少编程晶体管的尺寸。 编程使能电路用于允许在反熔丝的编程中使用具有较少位的编程地址移位寄存器。 公开了同时编程多个对应的反熔丝以加速ASIC编程的方法。 架构方面允许消除模块中的数字逻辑元件的输出保护，要消除一些测试晶体管，要降低其他测试晶体管的尺寸，减少互连线段上的电容，要消除的一些编程晶体管， 并减小其他编程晶体管的尺寸。

公开(公告)号：US5122685A

公开(公告)日：1992-06-16

申请号：US665103

申请日：1991-03-06

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six-input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

公开(公告)号：US4153938A

公开(公告)日：1979-05-08

申请号：US825648

申请日：1977-08-18

Applicant: Robert C. Ghest ,  Hua-Thye Chua ,  John M. Birkner

Inventor： Robert C. Ghest ,  Hua-Thye Chua ,  John M. Birkner

IPC: G06F7/52

CPC classification number: G06F7/5338 ,  G06F7/49963

Abstract: This disclosure relates to a high speed combinatorial 8 by 8 digital multiplier suitable for implementation on a single semiconductor chip including an encoder for implementing the Modified Booth Algorithm to encode the eight multiplier digits. The encoder includes five subsections which generate a plurality of control signals. Each of the plurality of control signals is inputted into a separate one of five multiplexor circuits each of which also receives inputs representative of eight multiplicand bits in accordance with implementation of the Modified Booth Algorithm. Each of the five multiplexer circuits provides a plurality of outputs, each of the pluralities of outputs representing a separate partial product of the multiplier and multiplicand inputs. The partial products are inputted to an array of carry-save adders. The final stage of the adder network includes a carry-look-ahead adder which produces sixteen outputs which represent the product of the multiplier and the multiplicand. The multiplier includes circuitry for permitting encoding of the multiplier inputs in either binary unsigned or in two's compliment form. A multiplier mode control input controls whether the multiplier inputs are operated upon as two's compliment or as unsigned binary numbers. Similarly, a mode control input to circuitry which generates the multiplexer inputs representative of the multiplicand also controls whether the multiplicand inputs are operated upon as two's compliment numbers or as unsigned binary numbers. The mode of the multiplier inputs and multiplicand inputs can be independently controlled, so that mixed signed and unsigned representations of the multiplier and multiplicand, respectively, can be utilized.

Abstract translation: 本公开涉及一种适用于在单个半导体芯片上实施的高速组合8×8数字乘法器，包括用于实现修改的布尔算法来编码八个乘法器数字的编码器。 编码器包括产生多个控制信号的五个子部分。 多个控制信号中的每一个被输入到五个多路复用器电路中的单独一个，每个复用器电路还根据修改的布尔算法的实现接收表示八个被乘数位的输入。 五个多路复用器电路中的每一个提供多个输出，多个输出中的每一个表示乘法器和被乘数输入的单独的部分乘积。 部分产品被输入到一个携带保存加法器阵列。 加法器网络的最后阶段包括进位前瞻加法器，其产生十六个输出，其表示乘法器和被乘数的乘积。 乘法器包括允许以二进制无符号或二进制补码形式对乘法器输入进行编码的电路。 乘法器模式控制输入控制乘法器输入是以二进制补码或无符号二进制数进行操作。 类似地，产生代表被乘数的多路复用器输入的电路的模式控制输入也可以控制被乘数输入是以二进制编号或无符号二进制数进行操作。 可以独立地控制乘法器输入和乘法器输入的模式，从而可以利用乘法器和被乘数的混合有符号和无符号表示。

公开(公告)号：US6150199A

公开(公告)日：2000-11-21

申请号：US405979

申请日：1999-09-27

Applicant: Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

Inventor： Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas ,  Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for for forming a field programmable gate array with antifuses.

Abstract translation: 在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。 非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。 在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。 在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。 在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。 选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。 还描述了用于形成具有反熔丝的现场可编程门阵列的方法。

公开(公告)号：US5780919A

公开(公告)日：1998-07-14

申请号：US646823

申请日：1996-05-21

Applicant: Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

Inventor： Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

IPC: H01L21/82 ,  H01L23/525 ,  H01L27/10 ,  H01L29/00

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: In one method for forming amorphous silicon antifuses with significantly reduced leakage current, a film of amorphous silicon is formed in a antifuse via between two electrodes. The amorphous silicon film is deposited using plasma enhanced chemical vapor deposition, preferably in an silane-argon environment and at a temperature between 200 and 500 degrees C., or reactively sputtered in a variety of reactive gases. In another method, an oxide layer is placed between two amorphous silicon film layers. In yet another method, one of the amorphous silicon film layers about the oxide layer is doped. In another embodiment, a layer of conductive, highly diffusible material is formed either on or under the amorphous silicon film. The feature size and thickness of the amorphous silicon film are selected to minimize further the leakage current while providing the desired programming voltage. A method also is described for forming a field programmable gate array with antifuses.

Abstract translation: 在形成具有显着降低的漏电流的非晶硅反熔丝的一种方法中，在两个电极之间的反熔丝通孔中形成非晶硅膜。 非晶硅膜使用等离子体增强化学气相沉积，优选在硅烷 - 氩气环境中并在200-500℃的温度下沉积，或者以各种反应性气体反应溅射。 在另一种方法中，将氧化物层放置在两个非晶硅膜层之间。 在另一种方法中，围绕氧化物层的非晶硅膜之一被掺杂。 在另一个实施例中，在非晶硅膜上或下形成导电的，高度可扩散的材料层。 选择非晶硅膜的特征尺寸和厚度，以在提供期望的编程电压的同时进一步最小化漏电流。 描述了用反熔丝形成现场可编程门阵列的方法。

公开(公告)号：US5717230A

公开(公告)日：1998-02-10

申请号：US323168

申请日：1994-10-13

Applicant: Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

Inventor： Hua-Thye Chua ,  Andrew K. Chan ,  John M. Birkner ,  Ralph G. Whitten ,  Richard L. Bechtel ,  Mammen Thomas

IPC: H01L23/525 ,  H01L27/02

CPC classification number: H01L23/5252 ,  H01L2924/0002

Abstract: A field programmable gate array has a programmable interconnect structure comprising metal signal conductors and metal-to-metal PECVD amorphous silicon antifuses. The metal-to-metal PECVD amorphous silicon antifuses have an unprogrammed resistance of at least 550 megaohms and a programmed resistance of under 200 ohms.

Abstract translation: 现场可编程门阵列具有包括金属信号导体和金属对金属PECVD非晶硅反熔丝的可编程互连结构。 金属对金属PECVD非晶硅反熔丝具有至少550兆欧姆的未编程电阻和低于200欧姆的编程电阻。

公开(公告)号：US5594364A

公开(公告)日：1997-01-14

申请号：US493981

申请日：1995-06-23

Applicant: Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

Inventor： Andrew K. Chan ,  John M. Birkner ,  Hua-Thye Chua

IPC: H03K3/356 ,  H03K17/00 ,  H03K19/173 ,  H03K19/177

CPC classification number: H03K19/17736 ,  H03K19/1737 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1774 ,  H03K19/1778 ,  H03K19/17792

Abstract: A field programmable gate array includes a programmable routing network, a programmable configuration network integrated with the programmable routing network; and a logic cell integrated with the programmable configuration network. The logic cell includes four two-input AND gates, two six input AND gates, three multiplexers, and a delay flipflop. The logic cell is a powerful general purpose universal logic building block suitable for implementing most TTL and gate array macrolibrary functions. A considerable variety of functions are realizable with one cell delay, including combinational logic functions as wide as thirteen inputs, all boolean transfer functions for up to three inputs, and sequential flipflop functions such as T, JK and count with carry-in.

Abstract translation: 现场可编程门阵列包括可编程路由网络，与可编程路由网络集成的可编程配置网络; 以及与可编程配置网络集成的逻辑单元。 逻辑单元包括四个双输入与门，两个六个输入与门，三个多路复用器和延迟触发器。 逻辑单元是一种强大的通用逻辑构建块，适用于实现大多数TTL和门阵列宏图程序功能。 相当多种功能可以通过一个单元延迟来实现，包括宽达十三个输入的组合逻辑功能，最多三个输入的所有布尔传递函数，以及顺序触发器功能，如T，JK和带进位的计数。

公开(公告)号：US5424655A

公开(公告)日：1995-06-13

申请号：US246527

申请日：1994-05-20

Applicant: Hua-Thye Chua

Inventor： Hua-Thye Chua

IPC: G11C17/18 ,  H03K19/177

CPC classification number: H03K19/17776 ,  G11C17/18 ,  H03K19/17704 ,  H03K19/17728 ,  H03K19/1778 ,  H03K19/17792

Abstract: A programmable ASIC architecture allows the size of programming transistors to be reduced along with other parts of the device as advances in processing technology are made. Programming enable circuits are used to allow a programming address shift register having fewer bits to be used in the programming of antifuses. Methods of simultaneously programming multiple corresponding antifuses to speed ASIC programming are disclosed. Aspects of the architecture allow output protection for digital logic elements in modules to be eliminated, some testing transistors to be eliminated, the sizes of other testing transistors to be reduced, capacitances on interconnect wire segments to be reduced, some programming transistors to be eliminated, and the sizes of other programming transistors to be reduced.

Abstract translation: 随着处理技术的进步，可编程ASIC架构允许与设备的其他部分一起减少编程晶体管的尺寸。 编程使能电路用于允许在反熔丝的编程中使用具有较少位的编程地址移位寄存器。 公开了同时编程多个对应的反熔丝以加速ASIC编程的方法。 架构方面允许消除模块中的数字逻辑元件的输出保护，要消除一些测试晶体管，要降低其他测试晶体管的尺寸，减少互连线段上的电容，要消除的一些编程晶体管， 并减小其他编程晶体管的尺寸。