公开(公告)号：US20250068952A1

公开(公告)日：2025-02-27

申请号：US18456208

申请日：2023-08-25

Applicant: Google LLC

Inventor： Nicholas Reinhard Zobrist ,  Kevin Chenghao Miao ,  Alex Opremcak ,  Ofer Naaman ,  Theodore Charles White ,  Daniel Sank

IPC: G06N10/40

Abstract: A quantum computing system includes a cryogenic chamber and an integrated circuit located in the chamber. The integrated circuit includes a substrate, a qubit formed on the substrate, and a dissipative element that is formed on the substrate and coupled to the qubit. When the qubit is tuned to a first flux value, the integrated circuit is enabled to perform quantum-computation operations on a set of quantum states of the qubit. The quantum states include a ground state and an excited state. When the qubit is tuned to a second flux value, the qubit is enabled to transfer energy associated with the excited state from the qubit to the dissipative element. Upon the energy transfer, the qubit is transitioned to the ground state. The dissipative element is enabled to dissipate the transferred energy to a portion of the substrate.

公开(公告)号：US12239027B2

公开(公告)日：2025-02-25

申请号：US18117918

申请日：2023-03-06

Applicant: Google LLC

Inventor： Brian James Burkett ,  Ofer Naaman ,  Anthony Edward Megrant ,  Theodore Charles White

IPC: H10N60/01 ,  G06N10/00 ,  H10N60/12 ,  H10N60/80

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.

公开(公告)号：US20240194661A1

公开(公告)日：2024-06-13

申请号：US18080729

申请日：2022-12-13

Applicant: Google LLC

Inventor： Zhimin Jamie Yao ,  Michael C. Hamilton ,  Marissa Giustina ,  Brian James Burkett ,  Theodore Charles White ,  Ofer Naaman

IPC: H01L25/00 ,  H01L23/00

CPC classification number: H01L25/50 ,  H01L24/81 ,  H01L24/13 ,  H01L2224/13109 ,  H01L2224/81815

Abstract: A method includes providing a first chip having a circuit element layer stack, the circuit element layer stack including a plurality of circuit elements distributed across a plurality of layers. The circuit element layer stack has a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers and a coherent device layer disposed on the circuit element layer stack. The method includes removing the sacrificial material.

公开(公告)号：US20240194532A1

公开(公告)日：2024-06-13

申请号：US18080715

申请日：2022-12-13

Applicant: Google LLC

Inventor： Zhimin Jamie Yao ,  Michael C. Hamilton ,  Marissa Giustina ,  Brian James Burkett ,  Theodore Charles White ,  Ofer Naaman

IPC: H01L21/822 ,  H01L21/02 ,  H01L21/311 ,  H01L21/768 ,  H01L23/00 ,  H01L25/07

CPC classification number: H01L21/8221 ,  H01L21/02505 ,  H01L21/02598 ,  H01L21/31127 ,  H01L21/7688 ,  H01L24/16 ,  H01L24/29 ,  H01L25/074 ,  B82Y10/00

Abstract: A method includes providing a first chip having a circuit element layer stack, the circuit element layer stack including a plurality of circuit elements distributed across a plurality of layers. The circuit element layer stack has a sacrificial material filling a space between the plurality of circuit elements in the plurality of layers and a coherent device layer disposed on the circuit element layer stack. The method includes removing the sacrificial material.

公开(公告)号：US20210336121A1

公开(公告)日：2021-10-28

申请号：US16964053

申请日：2019-07-25

Applicant: Google LLC

Inventor： Brian James Burkett ,  Ofer Naaman ,  Anthony Edward Megrant ,  Theodore Charles White

IPC: H01L39/24 ,  H01L39/02 ,  H01L39/22 ,  G06N10/00

Abstract: Methods, systems and apparatus for forming Josephson junctions with reduced stray inductance. In one aspect, a device includes a substrate; a first superconductor layer on the substrate; an insulator layer on the first superconductor layer; a second superconductor layer on the insulator layer, wherein the first superconductor layer, the insulator layer, and the second superconductor layer form a superconductor tunnel junction; and a third superconductor layer directly on a surface of the first superconductor layer and directly on a surface of the second superconductor layer to provide a first contact to the superconducting tunnel junction and a second contact to the superconductor tunnel junction, respectively.