Abstract:
The neuromorphic arithmetic device comprises an input monitoring circuit that outputs a monitoring result by monitoring that first bits of at least one first digit of a plurality of feature data and a plurality of weight data are all zeros, a partial sum data generator that skips an arithmetic operation that generates a first partial sum data corresponding to the first bits of a plurality of partial sum data in response to the monitoring result while performing the arithmetic operation of generating the plurality of partial sum data, based on the plurality of feature data and the plurality of weight data, and a shift adder that generates the first partial sum data with a zero value and result data, based on second partial sum data except for the first partial sum data among the plurality of partial sum data and the first partial sum data generated with the zero value.
Abstract:
Provided is an artificial neural network device including pre-synaptic neurons configured to generate a plurality of input spike signals, and a post-synaptic neuron configured to receive the plurality of input spike signals and to generate an output spike signal during a plurality of time periods, wherein the post-synaptic neuron respectively applies different weights in the plurality of time periods according to contiguousness with a reference time period in which input spike signals, which lead generation of the output spike signal from among the plurality of input spike signals, are received.
Abstract:
Provided is a convolutional neural network system. The system includes an input buffer configured to store an input feature, a parameter buffer configured to store a learning parameter, a calculation unit configured to perform a convolution layer calculation or a fully connected layer calculation by using the input feature provided from the input buffer and the learning parameter provided from the parameter buffer, and an output buffer configured to store an output feature outputted from the calculation unit and output the stored output feature to the outside. The parameter buffer provides a real learning parameter to the calculation unit at the time of the convolution layer calculation and provides a binary learning parameter to the calculation unit at the time of the fully connected layer calculation.
Abstract:
Provided is a convolution neural network system including an image database configured to store first image data, a machine learning device configured to receive the first image data from the image database and generate synapse data of a convolution neural network including a plurality of layers for image identification based on the first image data, a synapse data compressor configured to compress the synapse data based on sparsity of the synapse data, and an image identification device configured to store the compressed synapse data and perform image identification on second image data without decompression of the compressed synapse data.
Abstract:
Provided is a convolutional neural network system including a data selector configured to output an input value corresponding to a position of a sparse weight from among input values of input data on a basis of a sparse index indicating the position of a nonzero value in a sparse weight kernel, and a multiply-accumulate (MAC) computator configured to perform a convolution computation on the input value output from the data selector by using the sparse weight kernel.
Abstract:
Provided is a parallel processing device with one or more group processors, in which each of the one or more group processors includes a plurality of instance processors configured to process a kernel execution instance for a predetermined parallel program model-based kernel, each of the plurality of instance processors includes a register storing context reference information including an identifier of a group processor to which the instance processor belongs and an identifier of the instance processor, and each of the plurality of instance processors executes the kernel by reading execution context data, which is stored in a memory for execution of the kernel, using the context reference instance.
Abstract:
The present disclosure relates to a neuromorphic arithmetic device. The neuromorphic arithmetic device may include first and second synapse circuits, a charging/discharging circuit, a comparator, and a counter. The first synapse circuit may generate a first current by performing a first multiplication operation on a first PWM signal and a first weight, and the second synapse circuit may generate a second current by performing a second multiplication operation on a second PWM signal and a second weight. The charging/discharging circuit may store charges induced by the first current and the second current in a charging period, and may discharge the charges in a discharging period. The comparator may compare a voltage level of the charges discharged in the discharging period and a level of a reference voltage. The counter may count output pulses of an oscillator on the basis of a result of the comparison by the comparator.
Abstract:
A first communication device is provided. The first communication device modulates data to generate a first data symbol. The first communication device generates a first signal by using a first signal waveform allocated among a plurality of mutually orthogonal signal waveforms and the first data symbol. The first communication device outputs the first signal to a serial line connected to a second communication device.