公开(公告)号：US07214992B1

公开(公告)日：2007-05-08

申请号：US10974145

申请日：2004-10-27

申请人： Andy Strachan ,  Douglas Brisbin

发明人： Andy Strachan ,  Douglas Brisbin

IPC分类号： H01L27/088

CPC分类号： H01L21/823425 ,  H01L27/088

摘要： The drain breakdown voltage walk-in of a dual-source, dual-gate PMOS transistor is significantly reduced by utilizing source regions which have a width that is equal to or less than a width of the drain region. By utilizing source regions with widths that are equal to or less than the width of the drain region, the current density in the drain region is significantly reduced which reduces the number of hot charge carriers that are trapped at the silicon-to-silicon dioxide interface which, turn in, reduces the drain breakdown voltage walk-in rate.

摘要翻译： 通过利用具有等于或小于漏区宽度的宽度的源极区，双源双栅极PMOS晶体管的漏极击穿电压进入显着降低。 通过利用宽度等于或小于漏区宽度的源极区，漏极区域中的电流密度显着降低，这减少了被捕获在硅 - 二氧化硅界面处的热电荷载流子的数量 其中，导通，降低漏极击穿电压入门速率。

公开(公告)号：US07180140B1

公开(公告)日：2007-02-20

申请号：US10825833

申请日：2004-04-16

申请人： Douglas Brisbin ,  Andrew Strachan

发明人： Douglas Brisbin ,  Andrew Strachan

IPC分类号： H01L29/76

CPC分类号： H01L29/0847 ,  H01L29/7835

摘要： A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

摘要翻译： 可以根据本发明设计和制造PMOS器件以定位其漏极结击穿点和最大冲击电离点，以减少或消除漏极击穿电压。 在一些实施例中，漏极结击穿点和最大冲击电离点位于距离栅极足够远的位置，器件不会显示出显着的漏极击穿电压。 该器件可以是具有包括P型轻掺杂漏极（P-LDD）注入的扩展漏极区的高压功率晶体管，漏极结击穿和最大冲击电离点通过控制用于产生P的植入剂量来适当地定位 -LDD植入物。 本发明的其他方面是用于设计PMOS器件的方法，包括通过确定栅极的相对位置和漏极结击穿和最大冲击电离点中的至少一个来减少漏极击穿电压的走向，以及用于制造集成电路的方法，包括 本发明的PMOS器件的任何实施例。

公开(公告)号：US06727547B1

公开(公告)日：2004-04-27

申请号：US10266543

申请日：2002-10-08

申请人： Douglas Brisbin ,  Andy Strachan

发明人： Douglas Brisbin ,  Andy Strachan

IPC分类号： H01L2978

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/41758 ,  H01L29/7801

摘要： In a LDMOS transistor or matrix of transistors, hot carrier degradation effects are reduced by providing a ring drain and providing the ring drain with an overvoltage bias relative to the internal drain(s) of the LDMOS transistors.

摘要翻译： 在LDMOS晶体管或晶体管矩阵中，通过提供环路漏极并使环路漏极相对于LDMOS晶体管的内部漏极具有过压偏置来降低热载流子劣化效应。

公开(公告)号：US06566710B1

公开(公告)日：2003-05-20

申请号：US09942480

申请日：2001-08-29

申请人： Andy Strachan ,  Douglas Brisbin

发明人： Andy Strachan ,  Douglas Brisbin

IPC分类号： H01L2976

CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0847 ,  H01L29/1095 ,  H01L29/7802

摘要： The safe operating area of a high-voltage MOSFET, such as a lateral double-diffused MOS (LDMOS) transistor, is increased by using transistor cells with an X-shaped body contact region and four smaller source regions that adjoin the body contact region. The X-shaped body contact region lowers the parasitic base resistance of the transistor, thereby increasing the safe operating area of the transistor.

摘要翻译： 通过使用具有X形体接触区域的晶体管单元和与身体接触区域相邻的四个较小的源极区域，诸如横向双扩散MOS（LDMOS）晶体管的高压MOSFET的安全操作区域增加。 X形体接触区域降低晶体管的寄生基极电阻，从而增加晶体管的安全工作面积。