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    Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in
    2.
    发明授权
    Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in 有权
    用于设计和制造具有漏极结击穿点的PMOS器件的方法，用于降低漏极击穿电压

    公开(公告)号：US07560348B2

    公开(公告)日：2009-07-14

    申请号：US11705975

    申请日：2007-02-14

    申请人： Douglas Brisbin ,  Andrew Strachan

    发明人： Douglas Brisbin ,  Andrew Strachan

    IPC分类号： H01L21/336

    CPC分类号： H01L29/0847 ,  H01L29/7835

    摘要： A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

    摘要翻译： 可以根据本发明设计和制造PMOS器件以定位其漏极结击穿点和最大冲击电离点，以减少或消除漏极击穿电压。 在一些实施例中，漏极结击穿点和最大冲击电离点位于距离栅极足够远的位置，器件不会显示出显着的漏极击穿电压。 该器件可以是具有包括P型轻掺杂漏极（P-LDD）注入的扩展漏极区域的高压功率晶体管，漏极结击穿和最大冲击电离点通过控制用于产生P的植入剂量来适当地定位 -LDD植入物。 本发明的其他方面是用于设计PMOS器件的方法，包括通过确定栅极的相对位置和漏极结击穿和最大冲击电离点中的至少一个来减少漏极击穿电压的走向，以及用于制造集成电路的方法，包括 本发明的PMOS器件的任何实施例。

    Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in
    4.
    发明申请
    Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in 有权
    用于设计和制造具有漏极结击穿点的PMOS器件的方法，用于降低漏极击穿电压

    公开(公告)号：US20070264768A1

    公开(公告)日：2007-11-15

    申请号：US11705975

    申请日：2007-02-14

    申请人： Douglas Brisbin ,  Andrew Strachan

    发明人： Douglas Brisbin ,  Andrew Strachan

    IPC分类号： H01L21/8238

    CPC分类号： H01L29/0847 ,  H01L29/7835

    摘要： A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

    摘要翻译： 可以根据本发明设计和制造PMOS器件以定位其漏极结击穿点和最大冲击电离点，以减少或消除漏极击穿电压。 在一些实施例中，漏极结击穿点和最大冲击电离点位于距离栅极足够远的位置，器件不会显示出显着的漏极击穿电压。 该器件可以是具有包括P型轻掺杂漏极（P-LDD）注入的扩展漏极区域的高压功率晶体管，漏极结击穿和最大冲击电离点通过控制用于产生P的植入剂量来适当地定位 -LDD植入物。 本发明的其他方面是用于设计PMOS器件的方法，包括通过确定栅极的相对位置和漏极结击穿和最大冲击电离点中的至少一个来减少漏极击穿电压的走向，以及用于制造集成电路的方法，包括 本发明的PMOS器件的任何实施例。

    LDMOS transistor structure for improving hot carrier reliability
    5.
    发明授权
    LDMOS transistor structure for improving hot carrier reliability 有权
    LDMOS晶体管结构，用于提高热载流子的可靠性

    公开(公告)号：US06946706B1

    公开(公告)日：2005-09-20

    申请号：US10616381

    申请日：2003-07-09

    申请人： Douglas Brisbin ,  David Tsuei ,  Alexander H. Owens ,  Andy Strachan

    发明人： Douglas Brisbin ,  David Tsuei ,  Alexander H. Owens ,  Andy Strachan

    IPC分类号： H01L29/06 ,  H01L29/423 ,  H01L29/76 ,  H01L29/78

    CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/0878 ,  H01L29/0886 ,  H01L29/4238

    摘要： An LDMOS structure which provides for reduced hot carrier effects. The reduction in hot carrier effects is achieved by increasing the size of the drain region of the LDMOS relative to the size of the source region. The larger size of the drain region reduces the concentration of electrons entering the drain region. This reduction in the concentration of electrons reduces the number of impact ionizations, which in turn reduces the hot carrier effects. The overall performance of the LDMOS is improved by reducing the hot carrier effects.

    摘要翻译： 提供减少热载体效应的LDMOS结构。 通过增加LDMOS的漏极区域相对于源极区域的尺寸来实现热载流子效应的降低。 漏极区域的较大尺寸减小了进入漏极区域的电子的浓度。 电子浓度的这种降低减少了冲击电离的数量，这又降低了热载流子的影响。 通过减少热载体效应，提高了LDMOS的整体性能。

    LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability
    6.
    发明授权
    LDMOS transistor structure using a drain ring with a checkerboard pattern for improved hot carrier reliability 有权
    LDMOS晶体管结构使用带有棋盘图案的排水环，以提高热载体的可靠性

    公开(公告)号：US06548839B1

    公开(公告)日：2003-04-15

    申请号：US10079093

    申请日：2002-02-20

    申请人： Andrew Strachan ,  Douglas Brisbin

    发明人： Andrew Strachan ,  Douglas Brisbin

    IPC分类号： H01L2710

    CPC分类号： H01L29/7816 ,  H01L29/0696 ,  H01L29/41758

    摘要： An LDMOS array includes an array of alternating source regions and drain regions formed in a semiconductor substrate to define a checkerboard pattern of source and drain regions. A source contact is formed in electrical contact with each of the source regions in the array to connect the source regions in parallel. A drain contact is formed in electrical contact with each of the drain regions in the array to connect the drain regions in parallel. A drain ring is formed around the periphery of the checkerboard pattern and in electrical contact with the drain contact, providing redistribution of the current flow within the LDMOS array and thereby allowing safer hot carrier operation at higher biases than with the conventional layout.

    摘要翻译： LDMOS阵列包括形成在半导体衬底中的交替源极区和漏极区的阵列，以限定源区和漏区的棋盘图案。 源极触点形成为与阵列中的每个源极区域电接触以平行地连接源极区域。 漏极接触形成为与阵列中的每个漏极区域电接触以平行地连接漏极区域。 排水环形成在棋盘图形的周边周围并与漏极接触电接触，提供电流在LDMOS阵列内的再分配，从而允许比传统布局更高的偏压更安全的热载体操作。

    Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in
    7.
    发明授权
    Method for designing and manufacturing a PMOS device with drain junction breakdown point located for reduced drain breakdown voltage walk-in 有权
    用于设计和制造具有漏极结击穿点的PMOS器件的方法，用于降低漏极击穿电压

    公开(公告)号：US08086979B2

    公开(公告)日：2011-12-27

    申请号：US12480916

    申请日：2009-06-09

    申请人： Douglas Brisbin ,  Andrew Strachan

    发明人： Douglas Brisbin ,  Andrew Strachan

    IPC分类号： G06F17/50

    CPC分类号： H01L29/0847 ,  H01L29/7835

    摘要： A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

    摘要翻译： 可以根据本发明设计和制造PMOS器件以定位其漏极结击穿点和最大冲击电离点，以减少或消除漏极击穿电压。 在一些实施例中，漏极结击穿点和最大冲击电离点位于距离栅极足够远的位置，器件不会显示出显着的漏极击穿电压。 该器件可以是具有包括P型轻掺杂漏极（P-LDD）注入的扩展漏极区域的高压功率晶体管，漏极结击穿和最大冲击电离点通过控制用于产生P的植入剂量来适当地定位 -LDD植入物。 本发明的其他方面是用于设计PMOS器件的方法，包括通过确定栅极的相对位置和漏极结击穿和最大冲击电离点中的至少一个来减少漏极击穿电压的走向，以及用于制造集成电路的方法，包括 本发明的PMOS器件的任何实施例。

    Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays
    9.
    发明授权
    Method of monitoring process misalignment to reduce asymmetric device operation and improve the electrical and hot carrier performance of LDMOS transistor arrays 有权
    监测过程失准的方法，以减少不对称器件的工作，并改善LDMOS晶体管阵列的电气和热载流子性能

    公开(公告)号：US07718448B1

    公开(公告)日：2010-05-18

    申请号：US11139819

    申请日：2005-05-27

    申请人： Douglas Brisbin ,  Prasad Chaparala

    发明人： Douglas Brisbin ,  Prasad Chaparala

    IPC分类号： G01R31/26 ,  G06F17/18 ,  G06F17/50

    CPC分类号： H01L22/34 ,  H01L29/7835

    摘要： A number of modified lateral DMOS (LDMOS) transistor arrays are formed and tested to determine if a measured value, such as a series on-resistance, substrate current, breakdown voltage, and reliability, satisfies process alignment requirements. The modified LDMOS transistor arrays are similar to standard LDMOS transistor arrays such that the results of the modified LDMOS transistor arrays can be used to predict the results of the standard LDMOS transistor arrays.

    摘要翻译： 形成并测试了许多改进的横向DMOS（LDMOS）晶体管阵列，以确定诸如串联导通电阻，衬底电流，击穿电压和可靠性的测量值是否满足工艺对准要求。 修改后的LDMOS晶体管阵列类似于标准LDMOS晶体管阵列，使得修改后的LDMOS晶体管阵列的结果可用于预测标准LDMOS晶体管阵列的结果。

    Method for Designing and Manufacturing a PMOS Device with Drain Junction Breakdown Point Located for Reduced Drain Breakdown Voltage Walk-in
    10.
    发明申请
    Method for Designing and Manufacturing a PMOS Device with Drain Junction Breakdown Point Located for Reduced Drain Breakdown Voltage Walk-in 有权
    用于设计和制造具有漏极结点故障点的PMOS器件的方法，用于降低漏极击穿电压

    公开(公告)号：US20090254872A1

    公开(公告)日：2009-10-08

    申请号：US12480916

    申请日：2009-06-09

    申请人： Douglas Brisbin ,  Andrew Strachan

    发明人： Douglas Brisbin ,  Andrew Strachan

    IPC分类号： G06F17/50

    CPC分类号： H01L29/0847 ,  H01L29/7835

    摘要： A PMOS device can be designed and manufactured in accordance with the invention to locate its drain junction breakdown point and maximum impact ionization point to reduce or eliminate drain breakdown voltage walk-in. In some embodiments, the drain junction breakdown point and maximum impact ionization point are located sufficiently far from the gate that the device exhibits no significant drain breakdown voltage walk-in. The device can be a high voltage power transistor having an extended drain region including a P-type lightly doped drain (P-LDD) implant, with drain junction breakdown and maximum impact ionization points appropriately located by controlling the implant dose employed to produce the P-LDD implant. Other aspects of the invention are methods for designing a PMOS device including by determining relative locations of the gate and at least one of the drain junction breakdown and maximum impact ionization points to reduce drain breakdown voltage walk-in, and methods for manufacturing integrated circuits including any embodiment of the PMOS device of the invention.

    摘要翻译： 可以根据本发明设计和制造PMOS器件以定位其漏极结击穿点和最大冲击电离点，以减少或消除漏极击穿电压。 在一些实施例中，漏极结击穿点和最大冲击电离点位于距离栅极足够远的位置，器件不会显示出显着的漏极击穿电压。 该器件可以是具有包括P型轻掺杂漏极（P-LDD）注入的扩展漏极区域的高压功率晶体管，漏极结击穿和最大冲击电离点通过控制用于产生P的植入剂量来适当地定位 -LDD植入物。 本发明的其他方面是用于设计PMOS器件的方法，包括通过确定栅极的相对位置和漏极结击穿和最大冲击电离点中的至少一个来减少漏极击穿电压的走向，以及用于制造集成电路的方法，包括 本发明的PMOS器件的任何实施例。