公开(公告)号：US07108546B2

公开(公告)日：2006-09-19

申请号：US09886521

申请日：2001-06-20

Applicant: Charles A. Miller ,  Benjamin N. Eldridge

Inventor： Charles A. Miller ,  Benjamin N. Eldridge

IPC: H01R9/05

CPC classification number: G01R1/0466 ,  H01R13/025 ,  H01R13/40 ,  H01R2201/20

Abstract: An apparatus including a substrate having a plurality of through holes and a plurality of cables, including wires and/or coaxial cables, extending through respective ones of the plurality of through holes of the substrate. Each of the cables comprises a conductor and terminates about a surface of the substrate such that the conductors of respective ones of plurality of cables are planarly aligned and available for electrical contact. A system including a cable interface extending through respective ones of a plurality of through holes of a body of the interface; an interconnection component comprising a first plurality of contact points aligned with respective ones of conductors of the plurality of cables and a second plurality of contact points aligned to corresponding contact points of a device to be tested. Also, a method of routing signals through the conductors of the plurality of cables between electronic components.

公开(公告)号：US07005751B2

公开(公告)日：2006-02-28

申请号：US10410948

申请日：2003-04-10

Applicant: Igor Y. Khandros ,  Charles A. Miller ,  Stuart W. Wenzel

Inventor： Igor Y. Khandros ,  Charles A. Miller ,  Stuart W. Wenzel

IPC: H01L23/48

CPC classification number: H05K3/4007 ,  H01L24/13 ,  H01L24/72 ,  H01L24/81 ,  H01L2224/05001 ,  H01L2224/05027 ,  H01L2224/05548 ,  H01L2224/05568 ,  H01L2224/05573 ,  H01L2224/13 ,  H01L2224/13099 ,  H01L2224/73251 ,  H01L2224/81901 ,  H01L2924/00014 ,  H01L2924/01006 ,  H01L2924/01013 ,  H01L2924/01015 ,  H01L2924/01022 ,  H01L2924/01027 ,  H01L2924/01033 ,  H01L2924/01039 ,  H01L2924/01046 ,  H01L2924/01047 ,  H01L2924/01058 ,  H01L2924/01074 ,  H01L2924/01075 ,  H01L2924/01078 ,  H01L2924/01079 ,  H01L2924/01082 ,  H01L2924/014 ,  H01L2924/10253 ,  H01L2924/14 ,  H01L2924/19041 ,  H01L2924/3011 ,  H01L2924/3025 ,  H01L2924/351 ,  H01R12/57 ,  H01R43/007 ,  H05K3/326 ,  H05K2201/0133 ,  H05K2201/0367 ,  H05K2201/09909 ,  Y10T29/49147 ,  H01L2924/00 ,  H01L2224/16 ,  H01L2224/72 ,  H01L2224/05599 ,  H01L2224/05099

Abstract: A microelectronic spring contact for making electrical contact between a device and a mating substrate and method of making the same are disclosed. The spring contact has a compliant pad adhered to a substrate of the device and spaced apart from a terminal of the device. The compliant pad has a base adhered to the substrate, and side surfaces extending away from the substrate and tapering to a smaller end area distal from the substrate. A trace extends from the terminal of the device over the compliant pad to its end area. At least a portion of the compliant pad end area is covered by the trace, and a portion of the trace that is over the compliant pad is supported by the compliant pad. A horizontal microelectronic spring contact and method of making the same are also disclosed. The horizontal spring contact has a rigid trace attached at a first end to a terminal of a substrate. The trace is free from attachment at its second end, and extends from the terminal in a direction substantially parallel to a surface of the substrate to the second end. At least a distal portion of the trace extending to the second end is spaced apart from the surface of the substrate. The spaced-apart distal portion is flexible in a plane parallel to the substrate.

Abstract translation: 公开了一种用于在器件和匹配衬底之间进行电接触的微电子弹簧触点及其制造方法。 弹簧触点具有粘附到装置的基板并与装置的端子间隔开的柔性衬垫。 柔性衬垫具有粘附到衬底的基底，以及远离衬底延伸的侧表面，并且逐渐变细到远离衬底的较小端部区域。 迹线从器件的端子通过柔性焊盘延伸到其端部区域。 柔性焊盘端部区域的至少一部分被迹线覆盖，并且位于柔性焊盘上方的迹线的一部分由柔性焊盘支撑。 还公开了一种水平微电子弹簧触头及其制造方法。 水平弹簧触点具有在第一端附接到基板的端子的刚性迹线。 该迹线在其第二端处没有附着，并且从基板平行于基板的表面的方向从端子延伸到第二端。 至少延伸到第二端的迹线的远端部分与衬底的表面间隔开。 间隔开的远侧部分在平行于基底的平面中是柔性的。

公开(公告)号：US06949942B2

公开(公告)日：2005-09-27

申请号：US10725824

申请日：2003-12-01

Applicant: Benjamin N. Eldridge ,  Charles A. Miller

Inventor： Benjamin N. Eldridge ,  Charles A. Miller

IPC: G01R31/26 ,  G01R31/28 ,  G01R31/317 ,  G01R31/319 ,  G06F1/26 ,  H01L21/66 ,  G01R31/02

CPC classification number: G06F1/26 ,  G01R31/2851 ,  G01R31/31721 ,  G01R31/31905 ,  G01R31/31924

Abstract: A main power source supplies current through path impedance to a power terminal of an integrated circuit device under test (DUT). The DUT's demand for current at the power input terminal temporarily increases following edges of a clock signal applied to the DUT during a test as transistors within the IC switch in response to the clock signal edges. To limit variation (noise) in voltage at the power input terminal, an auxiliary power supply supplies an additional current pulse to the power input terminal to meet the increased demand during each cycle of the clock signal. The magnitude of the current pulse is a function of a predicted increase in current demand during that clock cycle, and of the magnitude of an adaption signal controlled by a feedback circuit provided to limit variation in voltage developed at the DUT's power input terminal.

Abstract translation: 主电源将电流通过路径阻抗提供给被测集成电路器件（DUT）的电源端子。 在测试期间，DUT对电源输入端的电流需求暂时增加了在测试期间施加到DUT的时钟信号的随后边缘，作为IC开关中的晶体管响应于时钟信号的边缘。 为了限制电源输入端子的电压变化（噪声），辅助电源为电源输入端子提供额外的电流脉冲，以满足在时钟信号的每个周期期间增加的需求。 电流脉冲的大小是在该时钟周期期间电流需求的预测增加以及由反馈电路控制的适配信号的大小的函数，以限制在DUT的功率输入端产生的电压变化。

公开(公告)号：US06784677B2

公开(公告)日：2004-08-31

申请号：US10406669

申请日：2003-04-02

Applicant: Charles A. Miller ,  John Matthew Long

Inventor： Charles A. Miller ,  John Matthew Long

IPC: G01R1073

CPC classification number: G01R31/31926 ,  G01R1/07378 ,  G01R31/318511 ,  G11C29/56 ,  G11C2029/2602 ,  H05K1/0216 ,  H05K1/023 ,  H05K1/0289 ,  H05K2201/09254 ,  Y10T29/49117

Abstract: An interconnect structure employs a closed-grid bus to link an integrated circuit tester channel to an array of input/output (I/O) pads on a semiconductor wafer so that the tester channel can concurrently communicate with all of the I/O pads. The interconnect structure includes a circuit board implementing an array of bus nodes, each corresponding to a separate one of the I/O pads. The circuit board includes at least two layers. Traces mounted on a first layer form a set of first daisy-chain buses, each linking all bus nodes of a separate row of the bus node array. Traces mounted on a second circuit board layer form a set of second daisy-chain buses, each linking all bus nodes of a separate column of the bus node array. Vias and other circuit board interconnect ends of the first and second daisy-chain buses so that they form the closed-grid bus. Each bus node is connected though a separate isolation resistor to a separate contact pad mounted on a surface of the circuit board. A set of spring contacts or probes link each contact pad to a separate one of the I/O pads on the wafer.

Abstract translation: 互连结构采用闭合栅格总线将集成电路测试器通道连接到半导体晶片上的输入/输出（I / O）焊盘阵列，使得测试仪通道可以同时与所有I / O焊盘通信。 互连结构包括实现总线节点阵列的电路板，每个总线节点对应于单独的一个I / O焊盘。 电路板包括至少两层。 安装在第一层上的轨迹形成一组第一个菊花链总线，每个链路总线连接总线节点阵列的单独行的所有总线节点。 安装在第二电路板层上的迹线形成一组第二菊花链总线，每条链路总线连接总线节点阵列的单独列的所有总线节点。 第一和第二菊花链总线的通路和其他电路板互连端，使得它们形成闭合栅格总线。 每个总线节点通过单独的隔离电阻器连接到安装在电路板表面上的单独的接触焊盘。 一组弹簧触点或探针将每个接触垫连接到晶片上的单独的I / O焊盘之间。

公开(公告)号：US06784674B2

公开(公告)日：2004-08-31

申请号：US10142549

申请日：2002-05-08

Applicant: Charles A. Miller

Inventor： Charles A. Miller

IPC: G01R3102

CPC classification number: G01R1/07378 ,  G01R1/06772 ,  G01R31/31905

Abstract: A probe board provides signal paths between an integrated circuit (IC) tester and probes accessing terminals on the surfaces of ICs formed on a semiconductor wafer for receiving test signals form the IC tester. A branching signal path within the probe board distributes a test signal produced by one channel of the IC tester to several probes. Resistors within the branching signal path resistively isolate the probes from one another so that a fault occurring at any one IC terminal will not affect the logic state of the test signal arriving at any other IC terminal. The isolation resistors are sized relative to signal path characteristic impedances so as to substantially minimize test signal reflections at the branch points.

Abstract translation: 探针板在集成电路（IC）测试器和探针之间提供信号路径，该探针访问半导体晶片上形成的IC表面上的端子，用于从IC测试仪接收测试信号。 探针板内的分支信号路径将由IC测试仪的一个通道产生的测试信号分配给多个探头。 分路信号路径内的电阻电阻使探针彼此隔离，使得任何一个IC端子发生的故障不会影响到达任何其他IC端子的测试信号的逻辑状态。 隔离电阻器相对于信号路径特性阻抗的尺寸设置成大致最小化分支点处的测试信号反射。

公开(公告)号：US06686754B2

公开(公告)日：2004-02-03

申请号：US10286062

申请日：2002-10-31

Applicant: Charles A. Miller

Inventor： Charles A. Miller

IPC: G01R106

CPC classification number: G01R1/073 ,  G01R1/06766 ,  G01R1/06772

Abstract: Described herein is a probe card assembly providing signal paths for conveying high frequency signals between bond pads of an integrated circuit (IC) and an IC tester. The frequency response of the probe card assembly is optimized by appropriately distributing, adjusting and impedance matching resistive, capacitive and inductive impedance values along the signal paths so that the interconnect system behaves as an appropriately tuned Butterworth or Chebyshev filter.

Abstract translation: 这里描述的是提供用于在集成电路（IC）和IC测试器的接合焊盘之间传送高频信号的信号路径的探针卡组件。 通过沿着信号路径适当地分布，调整和阻抗匹配电阻，电容和电感阻抗值来优化探针卡组件的频率响应，使得互连系统作为适当调节的巴特沃斯或切比雪夫滤波器。

公开(公告)号：US06480978B1

公开(公告)日：2002-11-12

申请号：US09260459

申请日：1999-03-01

Applicant: Richard S. Roy ,  Charles A. Miller

Inventor： Richard S. Roy ,  Charles A. Miller

IPC: G01R3128

CPC classification number: G11C29/56 ,  G01R31/31905 ,  G01R31/3193 ,  H01L2224/16225 ,  H01L2924/19107

Abstract: What is disclosed is a system for testing a plurality of integrated circuit devices under test (DUTs), that includes a tester having at least one set of tester input/output (I/O) lines, the tester providing data values for testing a single DUT on the set of tester I/O lines, and circuitry coupled to the set of tester I/O lines to receive the data values from the tester and to provide error values to the tester, the circuitry forwards the data values to each of the plurality of DUTs, the circuitry performs a first comparison of the values of two locations having corresponding addresses in different DUTs after reading from the locations, and in response generates the error values indicative of the first comparison. The circuitry may further perform a second comparison of the values of two different locations in the same DUT to generate further error values indicative of the second comparison.

Abstract translation: 所公开的是用于测试被测试的多个集成电路器件（DUT）的系统，其包括具有至少一组测试器输入/输出（I / O）线的测试器，该测试器提供用于测试单个 测试仪I / O线上的DUT，以及耦合到一组测试仪I / O线的电路，以从测试器接收数据值，并向测试者提供错误值，电路将数据值转发到每个 多个DUT，电路在从该位置读取之后对不同DUT中具有相应地址的两个位置的值执行第一比较，并且响应于产生指示第一比较的误差值。 该电路还可以执行相同DUT中的两个不同位置的值的第二比较，以产生指示第二比较的另外的误差值。

公开(公告)号：USD395007S

公开(公告)日：1998-06-09

申请号：US65615

申请日：1997-01-30

Applicant: Charles A. Miller ,  Norbert Hoell

Designer： Charles A. Miller ,  Norbert Hoell

公开(公告)号：US5734685A

公开(公告)日：1998-03-31

申请号：US582922

申请日：1996-01-03

Applicant: Daniel J. Bedell ,  Charles A. Miller

Inventor： Daniel J. Bedell ,  Charles A. Miller

IPC: H04L7/00 ,  H04L7/033

CPC classification number: H04L7/0337 ,  H04L7/0008 ,  H04L7/0037 ,  H04L7/0041

Abstract: A system for distributing synchronized clock signals to spatially distributed circuits includes a pair of transmission lines, each extending between first and second sites. The transmission lines are interconnected at the second site so that an outgoing clock signal traveling on the first transmission line from the first site to the second site returns to the first site on the second transmission line. Spatially distributed deskewing circuits tap the signal transmission lines between the first and second sites. A first delay circuit in each deskewing circuit detects the outgoing clock signal on the first transmission line and produces a local clock signal that lags the outgoing clock signal by an adjustable delay time. A similar second delay circuit in each deskewing circuit delays the local clock signal by a similar adjustable delay time to produce a local reference signal. A phase lock controller in each deskewing circuit adjusts the delay times of the delay circuits so that the local reference signal is phase locked to the returning clock signal on the second transmission line. When reference signals in all deskewing circuits are phase locked to the returning clock signal, their local clock signals have similar phases regardless of the spatial distribution of the deskewing circuits that generate them.

Abstract translation: 用于将同步时钟信号分配给空间分布式电路的系统包括一对传输线，每条传输线在第一和第二站点之间延伸。 传输线在第二位置处互连，使得在第一传输线上从第一站点行进到第二站点的输出时钟信号返回到第二传输线上的第一站点。 空间分布的歪斜电路分别在第一和第二站点之间的信号传输线路。 每个去歪斜电路中的第一延迟电路检测第一传输线上的输出时钟信号，并产生一个本地时钟信号，该本地时钟信号滞后于输出时钟信号一个可调节的延迟时间。 每个去歪斜电路中的类似的第二延迟电路使本地时钟信号延迟相似的可调延迟时间以产生局部参考信号。 每个去歪斜电路中的锁相控制器调节延迟电路的延迟时间，使得本地参考信号被锁相到第二传输线上的返回时钟信号。 当所有去偏置电路中的参考信号被锁相到返回时钟信号时，它们的本地时钟信号具有类似的相位，而不管生成它们的偏移电路的空间分布如何。

公开(公告)号：US5712883A

公开(公告)日：1998-01-27

申请号：US581000

申请日：1996-01-03

Applicant: Charles A. Miller ,  Daniel J. Bedell

Inventor： Charles A. Miller ,  Daniel J. Bedell

IPC: G01R31/319 ,  G06F1/10 ,  H03L7/07 ,  H03L7/081 ,  H04L7/00

CPC classification number: G01R31/31922 ,  G06F1/10 ,  H03L7/07 ,  H03L7/0812 ,  H04L7/0008

Abstract: A system for distributing synchronous clock signals includes a set of spatially distributed deskewing stages. Each stage includes matching adjustable first and second delay circuits and a phase lock loop controller. Matching pairs of transmission lines interconnect successive stages of the set. One transmission line of each pair connects the output of the first delay circuit of each stage to the input of the first delay circuit of a next stage of the set. The other transmission line of the pair connects the input of the second delay circuit of the stage to the input of the first delay circuit of the next stage. When the first delay circuit of the first stage of the set receives an input reference clock signal, that reference clock signal propagates through all the first delay circuits of each stage in succession. Whenever the input reference clock signal reaches a stage, it also travels back to the second delay circuit of the preceding stage. The phase lock loop controller in each stage adjusts the similar delay provided by its first and second delay circuits to phase lock the output second delay circuit to the input of the first delay circuit. Each stage also includes a frequency multiplier for doubling the frequency of its first input signal thereby to produce one of the spatially distributed local clock signals.

Abstract translation: 用于分配同步时钟信号的系统包括一组空间分布的去歪斜阶段。 每个级包括可调整的第一和第二延迟电路和一个锁相环控制器。 传输线的匹配对互连该组的连续阶段。 每对的一条传输线将每级的第一延迟电路的输出连接到该组的下一级的第一延迟电路的输入端。 该对的另一传输线将级的第二延迟电路的输入连接到下一级的第一延迟电路的输入。 当集合的第一级的第一延迟电路接收到输入参考时钟信号时，该参考时钟信号依次传播到每个级的所有第一延迟电路。 每当输入参考时钟信号达到一个阶段时，它也返回到前一级的第二延迟电路。 每个级中的锁相环控制器调节由其第一和第二延迟电路提供的类似延迟，以将输出第二延迟电路锁定到第一延迟电路的输入。 每个级还包括用于使其第一输入信号的频率加倍的倍频器，从而产生空间分布的本地时钟信号之一。