公开(公告)号：US11695079B2

公开(公告)日：2023-07-04

申请号：US17356167

申请日：2021-06-23

Applicant: BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Lizhong Wang ,  Tianmin Zhou ,  Hehe Hu ,  Xiaochun Xu ,  Nianqi Yao ,  Dapeng Xue ,  Shuilang Dong

IPC: H01L27/00 ,  H01L29/00 ,  H01L29/786 ,  H01L27/12 ,  H01L29/66

CPC classification number: H01L29/7869 ,  H01L27/127 ,  H01L27/1225 ,  H01L29/66969

Abstract: An oxide thin film transistor includes: a gate electrode, a metal oxide active layer and a source-drain metal layer, which are on a base substrate. The metal oxide active layer includes a first metal oxide layer and a second metal oxide layer stacked on the first metal oxide layer in a direction away from the base substrate; the first metal oxide layer is a carrier transport layer; the second metal oxide layer is a carrier isolation layer; an electron transfer rate of the carrier transport layer is greater than an electron transfer rate of the carrier isolation layer. The first metal oxide layer includes a primary surface facing toward the base substrate and a primary surface away from the base substrate; the first metal oxide layer further includes a lateral surface around the primary surfaces; the second metal oxide layer covers the lateral surface of the first metal oxide layer.

公开(公告)号：US20220399377A1

公开(公告)日：2022-12-15

申请号：US17594832

申请日：2020-12-21

Applicant: BEIJING BOE DISPLAY TECHNOLOGY CO., LTD. ,  BOE TECHNOLOGY GROUP CO., LTD.

Inventor： Chongyang Zhao ,  Yingmeng Miao ,  Zhihua Sun ,  Feng Qu ,  Xiaochun Xu

IPC: H01L27/12 ,  G02F1/1362

Abstract: An array substrate, a display panel, and an electronic device are provided. The array substrate includes: a base substrate; a first electrode arranged on the base substrate; a gate line arranged on the base substrate, wherein the gate line is electrically insulated from the first electrode; a second electrode arranged on a side of the gate line away from the base substrate, wherein at least one first sub-pixel unit provided on the base substrate includes: a first connection portion arranged in a same layer as the second electrode and a second connection portion arranged in a same layer as the gate line, wherein the second connection portion is electrically connected to the first electrode, and an orthographic projection of the second connection portion on the base substrate at least partially overlaps an orthographic projection of the first connection portion on the base substrate.

公开(公告)号：US20230021559A1

公开(公告)日：2023-01-26

申请号：US17770590

申请日：2021-03-15

Applicant: BOE Technology Group Co., Ltd.

Inventor： Yitong Guo ,  Jian Zhou ,  Tuo Sun ,  Xiaochun Xu

IPC: H01L27/12

Abstract: A back plate includes a base substrate, gate lines, data lines and power supply lines arranged on the base substrate crossing each other in rows and columns, and pixel structures arranged in an array on the base substrate, each pixel structure includes a driving transistor, a switching transistor connected thereto, and a pixel electrode connected thereto; a gate line and a data line are connected to the switching transistor, and a power supply line is connected to the driving transistor; in a same row or column of pixel structures, a power supply line is arranged between an (2n−1)th pixel structure and an 2n−th pixel structure, and the power supply line is connected to a source electrode of a driving transistor in the (2n−1)th pixel structure and a source electrode of a driving transistor in the 2n−th pixel structure; n is a positive integer greater than or equal to 1.

公开(公告)号：US20230006070A1

公开(公告)日：2023-01-05

申请号：US17782035

申请日：2021-05-27

Applicant: BOE Technology Group Co., Ltd.

Inventor： Jie Huang ,  Ce Ning ,  Zhengliang Li ,  Hehe Hu ,  Jiayu He ,  Nianqi Yao ,  Kun Zhao ,  Feng Qu ,  Xiaochun Xu

IPC: H01L29/786 ,  H01L29/66 ,  H01L27/12

Abstract: A semiconductor substrate manufacturing method and a semiconductor substrate. The manufacturing method includes: forming a first semiconductor layer on the base substrate at a first temperature with a first oxide semiconductor material; forming the second semiconductor layer directly on the first semiconductor layer with a second oxide semiconductor material; and performing a patterning process such that the first semiconductor layer and the second semiconductor layer are respectively patterned into a seed layer and a first channel layer. Both the first oxide semiconductor material and the second oxide semiconductor material are capable of forming crystalline phases at a second temperature, the second temperature is less than or equal to 40° C., and the first temperature is greater than or equal to 100° C.