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11.发明授权公开(公告)号：US11474633B2
公开(公告)日：2022-10-18
申请号：US17491127
申请日：2021-09-30
Applicant: BOE Technology Group Co., Ltd.
Inventor： Lubin Shi , Fuqiang Li , Fangzhen Zhang , Wei Qin
IPC: G06F3/041 , G06F3/0488 , G06F3/14 , G09G3/32 , G06F3/044
Abstract: The embodiments of the present application disclose a touch control display panel and a manufacturing method thereof, a touch control display screen and a spliced screen. The touch control display panel comprises: A substrate; A driving circuit layer, wherein the driving circuit layer comprises a driving line and a data line, a touch control row electrode and a touch control column electrode, the touch control row electrode is connected to at least one row auxiliary electrode via at least one first via hole, and each row of touch control row electrodes are connected to each other in series via the row auxiliary electrode; the touch control column electrode is connected to at least one column auxiliary electrode through at least one second via, and each column touch control column electrode is connected to each other in series through the column auxiliary electrode.
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12.发明授权公开(公告)号：US12170056B2
公开(公告)日：2024-12-17
申请号：US18509233
申请日：2023-11-14
Applicant: BOE Technology Group Co., Ltd.
Inventor： Ming Yang , Qi Qi , Wanzhi Chen , Lubin Shi , Fuqiang Li , Fei Wang
IPC: G09G3/32
Abstract: A light emitting substrate is provided. The light emitting substrate includes a plurality of light emitting controlling units arranged in M rows and N columns, M is an integer equal to or greater than one, N is an integer equal to or greater than one, wherein a respective one of the plurality of light emitting controlling units includes a plurality of light emitting elements arranged in J rows and I columns, J being an integer equal to or greater than one, I being an integer equal to or greater than one, a i-th column of the I columns of light emitting elements includes J rows of light emitting elements, 1≤i≤I; (M×J) number of first voltage signal lines; and (M×J) number of groups of second voltage signal lines.
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13.发明授权公开(公告)号：US11973166B2
公开(公告)日：2024-04-30
申请号：US17340672
申请日：2021-06-07
Applicant: BOE Technology Group Co., Ltd.
Inventor： Lubin Shi , Bin Qin , Liang Chen , Dongni Liu , Fangzhen Zhang , Ke Wang
IPC: H01L33/48 , H01L25/075
CPC classification number: H01L33/486 , H01L25/0753 , H01L2933/0016 , H01L2933/0066
Abstract: A displaying base plate and a fabricating method thereof. The displaying base plate includes a substrate, and a first flat layer on one side of the substrate; a first metal layer on one side of the first flat layer that is further away from the substrate; a second flat layer on sides of the first metal layer and the first flat layer that are further away from the substrate; and a second metal layer on one side of the second flat layer that is further away from the substrate; wherein the first metal layer includes a first metal trace, an orthographic projection of the second metal layer on the substrate and an orthographic projection of the first metal trace on the substrate have an overlapping part, and an orthographic projection of the second flat layer on the substrate covers the orthographic projection of the first metal trace on the substrate.
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Patent Agency Ranking
公开(公告)号：US11893942B2
公开(公告)日：2024-02-06
申请号：US16958822
申请日：2019-09-17
Applicant: BOE Technology Group Co., Ltd.
IPC: G09G3/3266
CPC classification number: G09G3/3266 , G09G2300/0408 , G09G2310/08 , G09G2330/021
Abstract: A GOA unit circuit is provided with an input sub-circuit configured to set a turn-on voltage to a first node and a turn-off voltage to a second node in response to an input signal and a first clock signal; a first pull-down sub-circuit, a pull-up sub-circuit, a first control sub-circuit, and a second control sub-circuit configured to set voltage levels of the first, the second, and a third nodes. The gate on array unit circuit also includes a first output sub-circuit to output a first output signal at the turn-on voltage triggered by a second clock in response to voltage levels at the first, second nodes and a second output sub-circuit to output a second output signal falling to the turn-off voltage triggered by the first clock and rising to the turn-on voltage triggered by the third clock in response to voltage levels at the first, third nodes.
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公开(公告)号：US11688351B2
公开(公告)日：2023-06-27
申请号：US17449008
申请日：2021-09-27
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Lubin Shi , Xiaohai Chen , Tingting Zhou
IPC: G09G3/3275 , G09G3/3266 , G11C19/28
CPC classification number: G09G3/3275 , G09G3/3266 , G11C19/28 , G09G2310/0286
Abstract: A shift register unit, a gate driving circuit, and a display device are provided. The shift register unit includes an input terminal, a first shift register sub-unit, and a second shift register sub-unit. The first shift register sub-unit includes a first output terminal, is connected to the input terminal to receive an input signal, and is configured to output a first output signal at the first output terminal according to the input signal; the second shift register sub-unit includes a second output terminal, is connected to the input terminal to receive the input signal, and is configured to output a second output signal at the second output terminal according to the input signal; and a pulse portion of the first output signal at least partially overlaps with a pulse portion of the second output signal in time.
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公开(公告)号：US20230142651A1
公开(公告)日：2023-05-11
申请号：US16958822
申请日：2019-09-17
Applicant: BOE Technology Group Co., Ltd.
IPC: G09G3/3266
CPC classification number: G09G3/3266 , G09G2300/0408 , G09G2310/08 , G09G2330/021
Abstract: A GOA unit circuit is provided with an input sub-circuit configured to set a turn-on voltage to a first node and a turn-off voltage to a second node in response to an input signal and a first clock signal; a first pull-down sub-circuit, a pull-up sub-circuit, a first control sub-circuit, and a second control sub-circuit configured to set voltage levels of the first, the second, and a third nodes. The gate on array unit circuit also includes a first output sub-circuit to output a first output signal at the turn-on voltage triggered by a second clock in response to voltage levels at the first, second nodes and a second output sub-circuit to output a second output signal falling to the turn-off voltage triggered by the first clock and rising to the turn-on voltage triggered by the third clock in response to voltage levels at the first, third nodes.
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17.发明授权公开(公告)号：US11636800B2
公开(公告)日：2023-04-25
申请号：US17489612
申请日：2021-09-29
Applicant: BOE Technology Group Co., Ltd.
Inventor： Lubin Shi , Fuqiang Li , Tingting Zhou
Abstract: A pixel circuit includes: a charge storage circuit with first and second terminals thereof electrically coupled to first and second nodes, respectively; a reset circuit with first, second and third control terminals thereof electrically coupled to a reference signal line, a first initialization signal line, and a second initialization signal line, respectively, with fourth, fifth and sixth terminals thereof electrically coupled to the first node, a cathode of a photodiode and the second node, respectively; a photosensitive control circuit with first, second and third terminals thereof electrically coupled to an anode of the photodiode, the first node and the second node, respectively; an output circuit with first and second terminals thereof electrically coupled to a first level terminal and a fourth terminal of the photosensitive control circuit, respectively.
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公开(公告)号：US11151946B2
公开(公告)日：2021-10-19
申请号：US16641970
申请日：2019-01-04
Applicant: BOE TECHNOLOGY GROUP CO., LTD.
Inventor： Lubin Shi , Xiaohai Chen , Tingting Zhou
IPC: G09G3/3275 , G09G3/3266 , G11C19/28
Abstract: A shift register unit and a driving method, a gate driving circuit, and a display device are provided. The shift register unit includes an input terminal, a first shift register sub-unit, and a second shift register sub-unit. The first shift register sub-unit includes a first output terminal, is connected to the input terminal to receive an input signal, and is configured to output a first output signal at the first output terminal according to the input signal; the second shift register sub-unit includes a second output terminal, is connected to the input terminal to receive the input signal, and is configured to output a second output signal at the second output terminal according to the input signal; and a pulse portion of the first output signal at least partially overlaps with a pulse portion of the second output signal in time.
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