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    Chip bonding method and bonding device
    4.
    发明授权
    Chip bonding method and bonding device 有权

    公开(公告)号：US11239198B2

    公开(公告)日：2022-02-01

    申请号：US16830834

    申请日：2020-03-26

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Lili Wang ,  Haiwei Sun ,  Zhenxing Tang ,  Feng Qu ,  Jing Liu ,  Chao Liu ,  Chuhang Wang ,  Qiangwei Cui ,  Ke Meng ,  Linhui Gong

    IPC: H01L23/00 ,  H01L25/18 ,  H01L25/00

    Abstract: A chip bonding method and a bonding device. The chip bonding method is used for bonding a chip to a display module, the display module includes a substrate and a functional layer on the substrate, the substrate includes a first substrate portion and a second substrate portion, the functional layer is on the first substrate portion, and an electrode is on an upper side of the second substrate portion. The chip bonding method includes: forming a light absorbing film layer on a side of the second substrate portion facing away from the electrode; coating a conductive adhesive film on the electrode, and placing the chip on the conductive adhesive film; and irradiating, by using a laser beam, a side of the second substrate portion facing away from the electrode.

    Array substrate and preparation method therefor, and display panel and display device
    5.
    发明授权
    Array substrate and preparation method therefor, and display panel and display device 有权

    公开(公告)号：US12230665B2

    公开(公告)日：2025-02-18

    申请号：US17264036

    申请日：2020-06-15

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Ke Meng ,  Qiangwei Cui ,  Chao Liu ,  Lili Wang ,  Chuhang Wang ,  Yutian Chu ,  Linhui Gong

    IPC: H01L27/15 ,  H01L33/00 ,  H01L33/62

    Abstract: An array substrate and a manufacturing method thereof, a display panel, and a display device are provided. The array substrate includes a bonding region and a non-bonding region, and further includes: a rigid substrate, in the non-bonding region; a driving circuit layer, in the non-bonding region; a light-emitting diode layer, on a side of the driving circuit layer away from the rigid substrate; a flexible base layer, in the bonding region and on the same side of the rigid substrate as the driving circuit layer; and a bonding wire layer, on a side of the flexible base layer away from the rigid substrate. The bonding wire layer and the flexible base layer is capable of being bent along an edge of the rigid substrate to a side of the rigid substrate away from the driving circuit layer.

    Micro-LED transfer method and display panel
    6.
    发明授权
    Micro-LED transfer method and display panel 有权

    公开(公告)号：US12033882B2

    公开(公告)日：2024-07-09

    申请号：US17295036

    申请日：2020-05-09

    Applicant: BOE TECHNOLOGY GROUP CO., LTD.

    Inventor： Lili Wang ,  Chuhang Wang ,  Chao Liu ,  Qiangwei Cui ,  Ke Meng ,  Linhui Gong

    IPC: H01L21/683 ,  H01L25/075 ,  H01L33/62

    CPC classification number: H01L21/6835 ,  H01L25/0753 ,  H01L33/62 ,  H01L2221/68354 ,  H01L2221/68368 ,  H01L2933/0066

    Abstract: A micro-LED transfer method, including: moving a passing substrate to a position above a donor substrate and moving the pasting substrate in a direction approaching the donor substrate to paste up LED grains so that the LED grains are separated from the bearing substrate; moving the pasting substrate with the LED grains to a position above a target substrate with the LED grains being closer to the target substrate than the pasting substrate, and conducting an alignment so that the LED grains are directly opposite to positions on the target substrate where the LED grains are to be arranged; and heating the pasting substrate with the LED grains to a first temperature greater than or equal to a melting temperature of the hot melt adhesive film to melt the hot melt adhesive film, so that the LED grains are separated from the pasting substrate and transferred to the target substrate.

    GOA unit circuit, driving method, GOA circuit, and display apparatus
    7.
    发明授权
    GOA unit circuit, driving method, GOA circuit, and display apparatus 有权

    公开(公告)号：US11893942B2

    公开(公告)日：2024-02-06

    申请号：US16958822

    申请日：2019-09-17

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Lubin Shi ,  Ke Meng

    IPC: G09G3/3266

    CPC classification number: G09G3/3266 ,  G09G2300/0408 ,  G09G2310/08 ,  G09G2330/021

    Abstract: A GOA unit circuit is provided with an input sub-circuit configured to set a turn-on voltage to a first node and a turn-off voltage to a second node in response to an input signal and a first clock signal; a first pull-down sub-circuit, a pull-up sub-circuit, a first control sub-circuit, and a second control sub-circuit configured to set voltage levels of the first, the second, and a third nodes. The gate on array unit circuit also includes a first output sub-circuit to output a first output signal at the turn-on voltage triggered by a second clock in response to voltage levels at the first, second nodes and a second output sub-circuit to output a second output signal falling to the turn-off voltage triggered by the first clock and rising to the turn-on voltage triggered by the third clock in response to voltage levels at the first, third nodes.

    GOA UNIT CIRCUIT, DRIVING METHOD, GOA CIRCUIT, AND DISPLAY APPARATUS
    8.
    发明公开
    GOA UNIT CIRCUIT, DRIVING METHOD, GOA CIRCUIT, AND DISPLAY APPARATUS 审中-公开

    公开(公告)号：US20230142651A1

    公开(公告)日：2023-05-11

    申请号：US16958822

    申请日：2019-09-17

    Applicant: BOE Technology Group Co., Ltd.

    Inventor： Lubin Shi ,  Ke Meng

    IPC: G09G3/3266

    CPC classification number: G09G3/3266 ,  G09G2300/0408 ,  G09G2310/08 ,  G09G2330/021

    Abstract: A GOA unit circuit is provided with an input sub-circuit configured to set a turn-on voltage to a first node and a turn-off voltage to a second node in response to an input signal and a first clock signal; a first pull-down sub-circuit, a pull-up sub-circuit, a first control sub-circuit, and a second control sub-circuit configured to set voltage levels of the first, the second, and a third nodes. The gate on array unit circuit also includes a first output sub-circuit to output a first output signal at the turn-on voltage triggered by a second clock in response to voltage levels at the first, second nodes and a second output sub-circuit to output a second output signal falling to the turn-off voltage triggered by the first clock and rising to the turn-on voltage triggered by the third clock in response to voltage levels at the first, third nodes.

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